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AD532JD-AD532JH-AD532KD-AD532KH-AD532SD-JM38510-JM38510/
Internally Trimmed Integrated Circuit Multiplier
Internally Trimmed
Integrated Circuit Multiplier
PIN CONFIGURATIONS
FEATURES
Pretrimmed to 61.0% (AD532K)
No External Components Required
Guaranteed 61.0% max 4-Quadrant Error (AD532K)
Diff Inputs for (X1 – X2) (Y1 – Y2)/10 V Transfer Function
Monolithic Construction, Low Cost
APPLICATIONS
Multiplication, Division, Squaring, Square Rooting
Algebraic Computation
Power Measurements
Instrumentation Applications
Available in Chip Form
PRODUCT DESCRIPTIONThe AD532 is the first pretrimmed single chip monolithic multi-
plier/divider. It guarantees a maximum multiplying error of1.0% and a –10 V output voltage without the need for any
external trimming resistors or output op amp. Because the
AD532 is internally trimmed, its simplicity of use provides
design engineers with an attractive alternative to modular multi-
pliers, and its monolithic construction provides significant ad-
vantages in size, reliability and economy. Further, the AD532
can be used as a direct replacement for other IC multipliers that
require external trim networks (such as the AD530).
FLEXIBILITY OF OPERATIONThe AD532 multiplies in four quadrants with a transfer func-
tion of (X1 – X2)(Y1 – Y2)/10 V, divides in two quadrants with
a 10 V Z/(X1 – X2) transfer function, and square roots in one
quadrant with a transfer function of –√10 V Z. In addition to
these basic functions, the differential X and Y inputs provide
significant operating flexibility both for algebraic computation and
transducer instrumentation applications. Transfer functions,
such as XY/10 V, (X2 – Y2)/10 V, –X2/10 V and 10 V Z/(X1 – X2),
are easily attained and are extremely useful in many modulation
and function generation applications, as well as in trigonometric
calculations for airborne navigation and guidance applications,
where the monolithic construction and small size of the AD532
offer considerable system advantages. In addition, the high
CMRR (75 dB) of the differential inputs makes the AD532
especially well qualified for instrumentation applications, as it
can provide an output signal that is the product of two transducer-
generated input signals.
GUARANTEED PERFORMANCE OVER TEMPERATUREThe AD532J and AD532K are specified for maximum multi-
plying errors of –2% and –1% of full scale, respectively at
+25°C, and are rated for operation from 0°C to +70°C. The
AD532S has a maximum multiplying error of –1% of full scale
at +25°C; it is also 100% tested to guarantee a maximum error
of –4% at the extended operating temperature limits of –55°C
and +125°C. All devices are available in either the hermetically-
sealed TO-100 metal can, TO-116 ceramic DIP or LCC packages.
J, K and S grade chips are also available.
ADVANTAGES OF ON-THE-CHIP TRIMMING OF THE
MONOLITHIC AD532True ratiometric trim for improved power supply rejection.Reduced power requirements since no networks across sup-
plies are required.More reliable since standard monolithic assembly techniques
can be used rather than more complex hybrid approaches.High impedance X and Y inputs with negligible circuit
loading.Differential X and Y inputs for noise rejection and additional
computational flexibility.
REV. B
AD532–SPECIFICATIONS(@ +258C, VS = 615 V, R ‡ 2 kV VOS grounded)DYNAMICS
NOISE
OUTPUT
INPUT AMPLIFIERS (X, Y and Z)
SQUARE ROOTER PERFORMANCE
POWER SUPPLY SPECIFICATIONS
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final
Thermal Characteristics
ORDERING GUIDE
CHIP DIMENSIONS AND BONDING DIAGRAMContact factory for latest dimensions.
Dimensions shown in inches and (mm).
Figure 1.Functional Block Diagram
FUNCTIONAL DESCRIPTIONThe functional block diagram for the AD532 is shown in Figure
1, and the complete schematic in Figure 2. In the multiplying
and squaring modes, Z is connected to the output to close the
feedback around the output op amp. (In the divide mode, it is
used as an input terminal.)
The X and Y inputs are fed to high impedance differential am-
plifiers featuring low distortion and good common-mode rejec-
tion. The amplifier voltage offsets are actively laser trimmed
to zero during production. The product of the two inputs is
resolved in the multiplier cell using Gilbert’s linearized trans-
conductance technique. The cell is laser trimmed to obtain
VOUT = (X1 – X2)(Y1 – Y2)/10 volts. The built-in op amp is used
to obtain low output impedance and make possible self-contained
operation. The residual output voltage offset can be zeroed at
VOS in critical applications . . . otherwise the VOS pin should be
grounded.
AD532
AD532 PERFORMANCE CHARACTERISTICSMultiplication accuracy is defined in terms of total error at
+25°C with the rated power supply. The value specified is in
percent of full scale and includes XIN and YIN nonlinearities,
feedback and scale factor error. To this must be added such
application-dependent error terms as power supply rejection,
common-mode rejection and temperature coefficients (although
worst case error over temperature is specified for the AD532S).
Total expected error is the rms sum of the individual compo-
nents since they are uncorrelated.
Accuracy in the divide mode is only a little more complex. To
achieve division, the multiplier cell must be connected in the
feedback of the output op amp as shown in Figure 13. In this
configuration, the multiplier cell varies the closed loop gain of
the op amp in an inverse relationship to the denominator volt-
age. Thus, as the denominator is reduced, output offset, band-
width and other multiplier cell errors are adversely affected. The
divide error and drift are then em · 10 V/X1 – X2) where em
represents multiplier full-scale error and drift, and (X1–X2) is
the absolute value of the denominator.
NONLINEARITYNonlinearity is easily measured in percent harmonic distortion.
The curves of Figures 3 and 4 characterize output distortion as
a function of input signal level and frequency respectively, with
one input held at plus or minus 10 V dc. In Figure 4 the sine
wave amplitude is 20 V (p-p).
Figure 3.Percent Distortion vs. Input Signal
AC FEEDTHROUGHAC feedthrough is a measure of the multiplier’s zero suppres-
sion. With one input at zero, the multiplier output should be
zero regardless of the signal applied to the other input. Feed-
through as a function of frequency for the AD532 is shown in
Figure 5. It is measured for the condition VX = 0, VY = 20 V
(p-p) and VY = 0, VX = 20 V (p-p) over the given frequency
range. It consists primarily of the second harmonic and is mea-
sured in millivolts peak-to-peak.
Figure 5.Feedthrough vs. Frequency
COMMON-MODE REJECTIONThe AD532 features differential X and Y inputs to enhance its
flexibility as a computational multiplier/divider. Common-mode
rejection for both inputs as a function of frequency is shown in
Figure 6. It is measured with X1 = X2 = 20 V (p-p), (Y1 – Y2) =
+10 V dc and Y1 = Y2 = 20 V (p-p), (X1 – X2) = +10 V dc.
Figure 6.CMRR vs. Frequency
DYNAMIC CHARACTERISTICSThe closed loop frequency response of the AD532 in the multi-
plier mode typically exhibits a 3 dB bandwidth of 1 MHz and
rolls off at 6 dB/octave thereafter. Response through all inputs is
essentially the same as shown in Figure 7. In the divide mode,
the closed loop frequency response is a function of the absolute
value of the denominator voltage as shown in Figure 8.
Stable operation is maintained with capacitive loads to 1000 pF
in all modes, except the square root for which 50 pF is a safe
upper limit. Higher capacitive loads can be driven if a 100 W
resistor is connected in series with the output for isolation.
Figure 8.Frequency Response, Dividing
POWER SUPPLY CONSIDERATIONSAlthough the AD532 is tested and specified with –15 V dc
supplies, it may be operated at any supply voltage from –10 V
to –18 V for the J and K versions, and –10 V to –22 V for the S
version. The input and output signals must be reduced propor-
tionately to prevent saturation; however, with supply voltages
below –15 V, as shown in Figure 9. Since power supply sensitiv-
ity is not dependent on external null networks as in the AD530
and other conventionally nulled multipliers, the power supply
rejection ratios are improved from 3 to 40 times in the AD532.
Figure 9.Signal Swing vs. Supply
NOISE CHARACTERISTICSAll AD532s are screened on a sampling basis to assure that
output noise will have no appreciable effect on accuracy. Typi-
cal spot noise vs. frequency is shown in Figure 10.
Figure 10.Spot Noise vs. Frequency
APPLICATIONS CONSIDERATIONSThe performance and ease of use of the AD532 is achieved
through the laser trimming of thin-film resistors deposited di-
rectly on the monolithic chip. This trimming-on-the-chip tech-
nique provides a number of significant advantages in terms of
cost, reliability and flexibility over conventional in-package
trimming of off-the-chip resistors mounted or deposited on a
hybrid substrate.
First and foremost, trimming on the chip eliminates the need
for a hybrid substrate and the additional bonding wires that are
required between the resistors and the multiplier chip. By trim-
ming more appropriate resistors on the AD532 chip itself, the
second input terminals that were once committed to external
trimming networks (e.g., AD530) have been freed to allow fully
differential operation at both the X and Y inputs. Further, the
requirement for an input attenuator to adjust the gain at the Y
input has been eliminated, letting the user take full advantage of
the high input impedance properties of the input differential
amplifiers. Thus, the AD532 offers greater flexibility for both
algebraic computation and transducer instrumentation
applications.
Finally, provision for fine trimming the output voltage offset has
been included. This connection is optional, however, as the
AD532 has been factory-trimmed for total performance as
described in the listed specifications.
REPLACING OTHER IC MULTIPLIERSExisting designs using IC multipliers that require external trim-
ming networks (such as the AD530) can be simplified using the
pin-for-pin replaceability of the AD532 by merely grounding
the X2, Y2 and VOS terminals. (The VOS terminal should always
be grounded when unused.)
AD532
APPLICATIONS
MULTIPLICATION
VOUT
+VS–VS
(OPTIONAL)
VOUT =(X1 – X2) (Y1 – Y2)
10VFigure 11.Multiplier Connection
For operation as a multiplier, the AD532 should be connected
as shown in Figure 11. The inputs can be fed differentially to
the X and Y inputs, or single-ended by simply grounding the
unused input. Connect the inputs according to the desired po-
larity in the output. The Z terminal is tied to the output to close
the feedback loop around the op amp (see Figure 1). The offset
adjust VOS is optional and is adjusted when both inputs are zero
volts to obtain zero out, or to buck out other system offsets.
SQUAREVOUT
+VS–VS
(OPTIONAL)
VOUT =VIN2
10VFigure 12.Squarer Connection
The squaring circuit in Figure 12 is a simple variation of the
multiplier. The differential input capability of the AD532, how-
ever, can be used to obtain a positive or negative output re-
sponse to the input...a useful feature for control applications,
as it might eliminate the need for an additional inverter somewhere
else.
DIVISION
VOUT
(X0)
+VS–VS
VOUT =10VZ
2.2kVFigure 13.Divider Connection
The AD532 can be configured as a two-quadrant divider by
connecting the multiplier cell in the feedback loop of the op
amp and using the Z terminal as a signal input, as shown in
Figure 13. It should be noted, however, that the output error is
given approximately by 10 V em/(X1 – X2), where em is the total
error specification for the multiply mode; and bandwidth by
fm · (X1 – X2)/10 V, where fm is the bandwidth of the multiplier.
single-ended positive inputs (0 V to +10 V), connect the input
to X2 and the offset null to X1. For optimum performance, gain
(S.F.) and offset (X0) adjustments are recommended as shown
and explained in Table I.
For practical reasons, the useful range in denominator input is
approximately 500 mV £ |(X1 – X2)| £ 10 V. The voltage offset
adjust (VOS), if used, is trimmed with Z at zero and (X1 – X2) at
full scale.
Table I.Adjust Procedure (Divider or Square Rooter)Repeat if required.
SQUARE ROOT
VOUT
(X0)
+VS–VS
2.2kVFigure 14.Square Rooter Connection
The connections for square root mode are shown in Figure 14.
Similar to the divide mode, the multiplier cell is connected in
the feedback of the op amp by connecting the output back to
both the X and Y inputs. The diode D1 is connected as shown
to prevent latch-up as ZIN approaches 0 volts. In this case, the
VOS adjustment is made with ZIN = +0.1 V dc, adjusting VOS to
obtain –1.0 V dc in the output, VOUT = – √10 V Z. For optimum
performance, gain (S.F.) and offset (X0) adjustments are recom-
mended as shown and explained in Table I.
DIFFERENCE OF SQUARESFigure 15.Differential of Squares Connection
The differential input capability of the AD532 allows for the
algebraic solution of several interesting functions, such as the
difference of squares, X2 – Y2/10 V. As shown in Figure 15, the
AD532 is configured in the square mode, with a simple unity
gain inverter connected between one of the signal inputs (Y)
