AD5326 Fast Delivery |IC PHOENIX CO.,LIMITED

AD5326 ,+2.5V to +5.5V, 400礎, 2-Wire Interface, Quad Voltage Output 12-Bit DACCHARACTERISTICS7Minimum Output Voltage 0.001 V This is a measure of the minimum and maximum drive7M ..
AD5326BRU ,+2.5V to +5.5V, 400µA, 2-Wire Interface, Quad Voltage Output 12-Bit DACCHARACTERISTICS7Minimum Output Voltage 0.001 0.001 V This is a measure of the minimumand maximum dr ..
AD5328ARU ,Octal 12-Bit Low Voltage Low Power Serial Vout DAC in 16 lead TSSOPGENERAL DESCRIPTIONA Version: 4 LSB INL, B Version: 3 LSB INLThe AD5308/AD5318/AD5328 are octal 8 ..
AD5328BRU , 2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
AD5328BRUZ-REEL7 , 2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
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AD9238BST-40 ,12-Bit, 20/40/65 MSPS Dual A/D Converterapplications in commu-nications, imaging, and medical ultrasound. 5. The patented SHA input maintai ..
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AD9238BSTZ-20 , 12-Bit, 20 MSPS/40 MSPS/65 MSPS Dual A/D Converter
AD9238BSTZ-40 , 12-Bit, 20 MSPS/40 MSPS/65 MSPS Dual A/D Converter
AD9238BSTZRL-20 , 12-Bit, 20 MSPS/40 MSPS/65 MSPS Dual A/D Converter

AD5326
2.5 V to 5.5 V, 400 礎, 2-Wire Interface Quad Voltage Output 8-Bit DAC
REV.B
FUNCTIONAL BLOCK DIAGRAMVOUTA
VDD
VOUTB
VOUTC
VOUTD
VREFA
SCL
LDAC
SDA
VREFB
VREFDVREFCGND
FEATURES
AD5306:Four Buffered 8-Bit DACs in 16-Lead TSSOP
AD5316:Four Buffered 10-Bit DACs in 16-Lead TSSOP
AD5326:Four Buffered 12-Bit DACs in 16-Lead TSSOP
Low Power Operation: 400 �A @ 3 V, 500 �A @ 5 V
2-Wire (I2C®-Compatible) Serial Interface
2.5 V to 5.5 V Power Supply
Guaranteed Monotonic By Design over All Codes
Power-Down to 90 nA @ 3 V, 300 nA @ 5 V (PD Pin or Bit)
Double-Buffered Input Logic
Buffered/Unbuffered Reference Input Options
Output Range: 0–VREF or 0–2 VREF
Power-On-Reset to Zero Volts
Simultaneous Update of Outputs (LDAC Pin)
Software Clear Facility
Data Readback Facility
On-Chip Rail-to-Rail Output Buffer Ampliﬁers
Temperature Range –40�C to +105�C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
GENERAL DESCRIPTION
The AD5306/AD5316/AD5326 are quad 8-, 10-, and 12-bit
buffered voltage output DACs, in a 16-lead TSSOP package, that
operate from a single 2.5 V to 5.5 V supply, consuming 500 µA
at 3 V. Their on-chip output amplifiers allow rail-to-rail output
swing with a slew rate of 0.7 V/µs. A 2-wire serial interface that
operates at clock rates up to 400 kHz is used. This interface is
SMBus-compatible at VDD < 3.6 V. Multiple devices can be placed
on the same bus.
Each DAC has a separate reference input that can be config-
ured as buffered or unbuffered. The outputs of all DACs may
be updated simultaneously using the asynchronous LDAC input.
The parts incorporate a power-on-reset circuit that ensures that
the DAC outputs power-up to zero volts and remain there until
a valid write to the device takes place. There is also a software clear
function that clears all DACs to 0 V. The parts contain a power-
down feature that reduces the current consumption of the device
to 300 nA @ 5 V (90 nA @ 3 V).
All three parts are offered in the same pinout, which allows users
to select the amount of resolution appropriate for their applica-
tion without redesigning their circuit board.
*. Patent Numbers 5,969,657 and 5,684,481.2C is a registered trademark of Philips Corporation.
2.5 V to 5.5 V, 400 �A, 2-Wire Interface,
Quad Voltage Output, 8-/10-/12-Bit DACs
AD5306/AD5316/AD5326–SPECIFICATIONS(VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 k� to
GND; CL = 200 pF to GND; all speciﬁcations TMIN to TMAX unless otherwise noted.)
AD5306/AD5316/AD5326
POWER REQUIREMENTS
NOTES
1See Terminology.
2Temperature range: B Version: –40°C to +105°C; typical at 25°C.DC speciﬁcations tested with the outputs unloaded.
4Linearity is tested using a reduced code range: AD5306 (Code 8 to 255); AD5316 (Code 28 to 1023); AD5326 (Code 115 to 4095).
5This corresponds to x codes. x = Deadband Voltage/LSB size.Guaranteed by design and characterization; not production tested.
7For the ampliﬁer output to reach its minimum voltage, Offset Error must be negative; for the ampliﬁer output to reach its maximum voltage, VREF = VDD and Offset plus Gain
Error must be positive.Interface inactive; all DACs active. DAC outputs unloaded.
Speciﬁcations subject to change without notice.
AC CHARACTERISTICS1
Slew Rate
Major-Code Change Glitch Energy
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
NOTESGuaranteed by design and characterization; not production tested.See Terminology.Temperature range: B Version: –40°C to +105°C; typical at 25°C.
Speciﬁcations subject to change without notice.
(VDD = 2.5 V to 5.5 V; RL = 2 k� to GND; CL = 200 pF to GND; all speciﬁcations TMIN to TMAX unless
otherwise noted.)
AD5306/AD5316/AD5326
TIMING CHARACTERISTICS1
NOTES
1See Figure 1.
2 Guaranteed by design and characterization; not production tested.
3A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
4Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.
Specifications subject to change without notice.
Figure 1.2-Wire Serial Interface Timing Diagram
(VDD = 2.5 V to 5.5 V; all speciﬁcations TMIN to TMAX unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = 25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
SCL, SDA to GND . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
A0, A1, LDAC, PD to GND . . . . . . . . –0.3 V to VDD + 0.3 V
Reference Input Voltage to GND . . . . –0.3 V to VDD + 0.3 V
VOUTA–D to GND . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . 150°C
16-Lead TSSOP Package
Power Dissipation . . . . . . . . . . . . . . . . . . (TJ max – TA)/θJA
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . 150.4°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5306/AD5316/AD5326 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this speciﬁcation is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
AD5306/AD5316/AD5326
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
TERMINOLOGY
RELATIVE ACCURACY
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
Typical INL versus Code plots can be seen in TPCs 1, 2, and 3.
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A speciﬁed differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed mono-
tonic by design. Typical DNL versus Code plots can be seen in
TPCs 4, 5, and 6.
OFFSET ERROR
This is a measure of the offset error of the DAC and the output
ampliﬁer. It can be positive or negative. See Figures 2 and 3. It
is expressed in mV.
GAIN ERROR
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.
OFFSET ERROR DRIFT
This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
GAIN ERROR DRIFT
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
DC POWER-SUPPLY REJECTION RATIO (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in dBs. VREF is held at 2 V and VDD is varied ±10%.
DC CROSSTALK
This is the dc change in the output level of one DAC at midscale
in response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of another DAC. It is expressed in µV.
REFERENCE FEEDTHROUGH
This is the ratio of the amplitude of the signal at the DAC
output to the reference input when the DAC output is not being
updated (i.e., LDAC is high). It is expressed in dBs.
CHANNEL-TO-CHANNEL ISOLATION
This is the ratio of the amplitude of the signal at the output of
one DAC to a sine wave on the reference input of another DAC.
It is measured in dBs.
MAJOR-CODE TRANSITION GLITCH ENERGY
Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC
register changes state. It is normally speciﬁed as the area of the
glitch in nV secs and is measured when the digital code is changed
by 1 LSB at the major carry transition (011...11 to 100...00
or 100...00 to 011...11).
DIGITAL FEEDTHROUGH
Digital feedthrough is a measure of the impulse injected into the
analog output of a DAC from the digital input pins of the device,
when the DAC output is not being updated. It is specified in
nV secs and is measured with a worst-case change on the digital
input pins, i.e., from all 0s to all 1s or vice versa.
DIGITAL CROSSTALK
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
expressed in nV secs.
ANALOG CROSSTALK
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured by
loading one of the DACs with a full-scale code change (all 0s to
all 1s and vice versa) while keeping LDAC high. Then pulse LDAC
low and monitor the output of the DAC whose digital code was
not changed. The energy of the glitch is expressed in nV secs.
DAC-TO-DAC CROSSTALK
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk. It
is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with LDAC low and moni-
toring the output of another DAC. The energy of the glitch is
expressed in nV secs.
MULTIPLYING BANDWIDTH
The ampliﬁers within the DAC have a ﬁnite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at which
the output amplitude falls to 3 dB below the input.
TOTAL HARMONIC DISTORTION
This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC, and the THD is a measure of the harmonics present
on the DAC output. It is measured in dBs.
AD5306/AD5316/AD5326
Figure 2.Transfer Function with Negative Offset
Figure 3.Transfer Function with Positive Offset (VREF = VDD)
TPC 1.AD5306 Typical INL Plot
TPC 4.AD5306 Typical DNL Plot
TPC 7.AD5306 INL and DNL
Error vs. VREF
CODE
INL ERROR
LSBs2001000400600800
TPC 2.AD5316 Typical INL Plot
CODE
DNL ERROR
LSBs
2000
TPC 5.AD5316 Typical DNL Plot
TEMPERATURE – �C
ERROR
LSBs
–0.5�40040
0.4
TPC 8.AD5306 INL and DNL
Error vs. Temperature
CODE
INL ERROR
LSBs4000100020003000
–12
TPC 3.AD5326 Typical INL Plot
CODE
DNL ERROR
LSBs
10000
TPC 6.AD5326 Typical DNL Plot
TEMPERATURE – �C
ERROR
% FSR
0.5�40040
–0.5120
TPC 9.AD5306 Offset Error and
Gain Error vs. Temperature
AD5306/AD5316/AD5326

VDD – Volts
ERROR
% FSR
0.1
TPC 10.Offset Error and Gain
Error vs. VDD
TPC 13.Supply Current vs. Supply
Voltage
TPC 16.Half-Scale Settling (1/4 to 3/4
Scale Code Change)

TPC 11.VOUT vs. Source and Sink
Current Capability
VDD – Volts
2.53.04.04.55.53.55.0
TPC 14.Power-Down Current vs.
Supply Voltage
TPC 17.Power-On Reset to 0 V
CODE
IDD
ZERO-SCALEFULL-SCALE
100
TPC 12.Supply Current vs. DAC Code
TPC 15.Supply Current vs. Logic
Input Voltage for SDA and SCL Volt-
age Increasing and Decreasing
TPC 18.Exiting Power-Down to
Midscale

Partno	Mfg	Dc	Qty	Available	Descript
AD5326	AD	N/a	9	avai	+2.5V to +5.5V, 400礎, 2-Wire Interface, Quad Voltage Output 12-Bit DAC