AD5316ARU-AD5316BRU-AD5326BRU Fast Delivery |IC PHOENIX CO.,LIMITED

AD5326BRU ,+2.5V to +5.5V, 400µA, 2-Wire Interface, Quad Voltage Output 12-Bit DACCHARACTERISTICS7Minimum Output Voltage 0.001 0.001 V This is a measure of the minimumand maximum dr ..
AD5328ARU ,Octal 12-Bit Low Voltage Low Power Serial Vout DAC in 16 lead TSSOPGENERAL DESCRIPTIONA Version: 4 LSB INL, B Version: 3 LSB INLThe AD5308/AD5318/AD5328 are octal 8 ..
AD5328BRU , 2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
AD5328BRUZ-REEL7 , 2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
AD532JD ,Internally Trimmed Integrated Circuit MultiplierSPECIFICATIONS AD532J AD532K AD532SModel Min Typ Max Min Typ Max Min Typ Max UnitsMULTIPLIER PERFO ..
AD532JD/+ ,Internally Trimmed Integrated Circuit MultiplierSPECIFICATIONS S OS AD532J AD532K AD532SModel Min Typ Max Min Typ Max Min Typ Max UnitMULTIPLIER P ..
AD9238BST-65 ,12-Bit, 20/40/65 MSPS Dual A/D ConverterSPECIFICATIONS ..
AD9238BSTRL-20 ,12-Bit, 20/40/65 MSPS Dual A/D ConverterSPECIFICATIONS1.0 V Internal Reference, T to T , un less oth er wise noted.)MIN MAX ..
AD9238BSTZ-20 , 12-Bit, 20 MSPS/40 MSPS/65 MSPS Dual A/D Converter
AD9238BSTZ-40 , 12-Bit, 20 MSPS/40 MSPS/65 MSPS Dual A/D Converter
AD9238BSTZRL-20 , 12-Bit, 20 MSPS/40 MSPS/65 MSPS Dual A/D Converter
AD9238BSTZRL-65 , 12-Bit, 20 MSPS/40 MSPS/65 MSPS Dual A/D Converter

AD5316ARU-AD5316BRU-AD5326BRU
2.5 V to 5.5 V, 400 µA, 2-Wire Interface Quad Voltage Output 8-Bit DAC
REV.C
2.5 V to 5.5 V, 400 �A, 2-Wire Interface,
Quad Voltage Output, 8-/10-/12-Bit DACs
*. Patent Numbers 5,969,657 and 5,684,481.
FEATURES
AD5306: 4 Buffered 8-Bit DACs in 16-Lead TSSOP
A Version: �1 LSB INL, B Version: �0.625 LSB INL
AD5316: 4 Buffered 10-Bit DACs in 16-Lead TSSOP
A Version: �4 LSB INL, B Version: �2.5 LSB INL
AD5326: 4 Buffered 12-Bit DACs in 16-Lead TSSOP
A Version: �16 LSB INL, B Version: �10 LSB INL
Low Power Operation: 400 �A @ 3 V, 500 �A @ 5 V
2-Wire (I2C® Compatible) Serial Interface
2.5 V to 5.5 V Power Supply
Guaranteed Monotonic by Design over All Codes
Power-Down to 90 nA @ 3 V, 300 nA @ 5 V (PD Pin
or Bit)
Double-Buffered Input Logic
Buffered/Unbuffered Reference Input Options
Output Range: 0 V to VREF or 0 V to 2 VREF
Power-On Reset to 0 V
Simultaneous Update of Outputs (LDAC Pin)
Software Clear Facility
Data Readback Facility
On-Chip Rail-to-Rail Output Buffer Ampliﬁers
Temperature Range –40�C to +105�C
FUNCTIONAL BLOCK DIAGRAMVOUTA
VDD
VOUTB
VOUTC
VOUTD
VREFA
SCL
LDAC
SDA
VREFB
VREFDVREFCGND
GENERAL DESCRIPTION
The AD5306/AD5316/AD5326 are quad 8-, 10-, and 12-bit
buffered voltage output DACs in a 16-lead TSSOP that operate
from a single 2.5 V to 5.5 V supply, consuming 500 µA at 3 V.
Their on-chip output amplifiers allow rail-to-rail output swing with
a slew rate of 0.7 V/µs. A 2-wire serial interface that operates at
clock rates up to 400 kHz is used. This interface is SMBus
compatible at VDD < 3.6 V. Multiple devices can be placed on
the same bus.
Each DAC has a separate reference input that can be configured
as buffered or unbuffered. The outputs of all DACs may be
updated simultaneously using the asynchronous LDAC input.
The parts incorporate a power-on reset circuit, which ensures
that the DAC outputs power up to 0 V and remain there until a
valid write to the device takes place. There is also a software
clear function that clears all DACs to 0 V. The parts contain a
power-down feature that reduces the current consumption of
the device to 300 nA @ 5 V (90 nA @ 3 V).
All three parts are offered in the same pinout, which allows
users to select the amount of resolution appropriate for their
application without redesigning their circuit board.
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
AD5306/AD5316/AD5326–SPECIFICATIONS(VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 k� to
GND; CL = 200 pF to GND; all speciﬁcations TMIN to TMAX, unless otherwise noted.)
DC PERFORMANCE
OUTPUT CHARACTERISTICS
LOGIC INPUTS
(Excluding SCL, SDA)
AD5306/AD5316/AD5326
AC CHARACTERISTICS1
LOGIC INPUTS (SCL, SDA)
POWER REQUIREMENTS
NOTESSee the Terminology section.Temperature range (A, B Version): –40∞C to +105∞C; typical at +25∞C.DC speciﬁcations tested with the outputs unloaded.Linearity is tested using a reduced code range: AD5306 (Code 8 to 255); AD5316 (Code 28 to 1023); AD5326 (Code 115 to 4095).This corresponds to x codes. x = deadband voltage/LSB size.Guaranteed by design and characterization; not production tested.For the ampliﬁer output to reach its minimum voltage, offset error must be negative; for the ampliﬁer output to reach its maximum voltage, VREF = VDD and offset
plus gain error must be positive.Interface inactive; all DACs active. DAC outputs unloaded.
Speciﬁcations subject to change without notice.
(VDD = 2.5 V to 5.5 V; RL = 2 k� to GND; CL = 200 pF to GND; all speciﬁcations TMIN to TMAX, unless
otherwise noted.)
AD5306/AD5316/AD5326
TIMING CHARACTERISTICS1 (VDD = 2.5 V to 5.5 V; all speciﬁcations TMIN to TMAX, unless otherwise noted.)
t10
t11
t12
t13
NOTESSee Figure 1.Guaranteed by design and characterization; not production tested.A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.
Specifications subject to change without notice.
Figure 1. 2-Wire Serial Interface Timing Diagram
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5306/AD5316/AD5326 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = 25∞C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
SCL, SDA to GND . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
A0, A1, LDAC, PD to GND . . . . . . . . –0.3 V to VDD + 0.3 V
Reference Input Voltage to GND . . . . –0.3 V to VDD + 0.3 V
VOUTA–D to GND . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (A, B Version) . . . . . . . . . . . . . –40∞C to +105∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . . 150∞C
ORDERING GUIDE
Model
16-Lead TSSOP
Power Dissipation . . . . . . . . . . . . . . . . . . (TJ max – TA)/�JA
�JA Thermal Impedance . . . . . . . . . . . . . . . . . . . 150.4∞C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C
Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this speciﬁcation is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
AD5306/AD5316/AD5326
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
3VOUTABuffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
4VOUTBBuffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
5VOUTCBuffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
6VREFAReference Input Pin for DAC A. It may be configured as a buffered or an unbuffered input depending on
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSB, from a straight
line passing through the endpoints of the DAC transfer function.
Typical INL versus code plots can be seen in TPCs 1, 2, and 3.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A speciﬁed differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. Typical DNL versus code plots can be
seen in TPCs 4, 5, and 6.
Offset Error
This is a measure of the offset error of the DAC and the output
ampliﬁer. It can be positive or negative. See Figures 2 and 3. It
is expressed in mV.
Gain Error
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.
Offset Error Drift
This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/∞C.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/∞C.
DC Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT
to a change in VDD for full-scale output of the DAC. It is mea-
sured in dB. VREF is held at 2 V and VDD is varied ±10%.
DC Crosstalk
This is the dc change in the output level of one DAC at midscale
in response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of another DAC. It is expressed in mV.
Reference Feedthrough
This is the ratio of the amplitude of the signal at the DAC out-
put to the reference input when the DAC output is not being
updated (i.e., LDAC is high). It is expressed in dB.
Channel-to-Channel Isolation
This is the ratio of the amplitude of the signal at the output of
one DAC to a sine wave on the reference input of another DAC. It
is measured in dB.
Major-Code Transition Glitch Energy
Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC regis-
ter changes state. It is normally speciﬁed as the area of the glitch
in nV-s and is measured when the digital code is changed by
1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or
100 . . . 00 to 011 . . . 11).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of a DAC from the digital input pins of the device
when the DAC output is not being updated. It is specified in
nV-s and is measured with a worst-case change on the digital
input pins, i.e., from all 0s to all 1s or vice versa.
Digital Crosstalk
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
expressed in nV-s.
Analog Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured by
loading one of the DACs with a full-scale code change (all 0s to
all 1s and vice versa) while keeping LDAC high. Then pulse
LDAC low and monitor the output of the DAC whose digital code
was not changed. The energy of the glitch is expressed in nV-s.
DAC-to-DAC Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk. It
is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with LDAC low and moni-
toring the output of another DAC. The energy of the glitch is
expressed in nV-s.
Multiplying Bandwidth
The ampliﬁers within the DAC have a ﬁnite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at which
the output amplitude falls to 3 dB below the input.
Total Harmonic Distortion
This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC, and the THD is a measure of the harmonics present
on the DAC output. It is measured in dB.
AD5306/AD5316/AD5326
Figure 2. Transfer Function with Negative Offset
Figure 3. Transfer Function with Positive Offset
(VREF = VDD)
TPC 1.AD5306 Typical INL Plot
TPC 4.AD5306 Typical DNL Plot
TPC 7.AD5306 INL and DNL
Error vs. VREF
TPC 2.AD5316 Typical INL Plot
CODE
DNL ERROR (LSB)
2000
TPC 5.AD5316 Typical DNL Plot
TEMPERATURE (�C)
ERROR (LSB)
–0.5�40040
0.4
TPC 8.AD5306 INL and DNL
Error vs. Temperature
TPC 3.AD5326 Typical INL Plot
CODE
DNL ERROR (LSB)
10000
TPC 6.AD5326 Typical DNL Plot
TPC 9.AD5306 Offset Error and
Gain Error vs. Temperature
AD5306/AD5316/AD5326
TPC 10.Offset Error and
Gain Error vs. VDD
TPC 13. Supply Current vs.
Supply Voltage
TPC 16.Half-Scale Settling (1/4 to
3/4 Scale Code Change)
TPC 11. VOUT vs. Source and
Sink Current Capability
VDD (V)
+25�C
TPC 14.Power-Down Current vs.
Supply Voltage
TPC 17.Power-On Reset to 0 V
TPC 12.Supply Current vs.
DAC Code
TPC 15.Supply Current vs. Logic
Input Voltage for SDA and SCL
Voltage Increasing and Decreasing
TPC 18.Exiting Power-Down
to Midscale

Partno	Mfg	Dc	Qty	Available	Descript
AD5316ARU	AD	N/a	6	avai	2.5 V to 5.5 V, 400 µA, 2-Wire Interface Quad Voltage Output 10-Bit DAC
AD5316BRU	AD	N/a	3	avai	2.5 V to 5.5 V, 400 µA, 2-Wire Interface Quad Voltage Output 10-Bit DAC
AD5326BRU	AD	N/a	390	avai	+2.5V to +5.5V, 400µA, 2-Wire Interface, Quad Voltage Output 12-Bit DAC