AD5313BRU-AD5323BRU Fast Delivery |IC PHOENIX CO.,LIMITED

AD5313BRU ,+2.5 V to +5.5 V, 230 uA, Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACsFEATURESThe AD5303/AD5313/AD5323 are dual 8-, 10- and 12-bitAD5303: Two Buffered 8-Bit DACs in One ..
AD5314BRM ,2.5 V to 5.5 V, 500 uA, Quad Voltage Output 8-/10-/12-Bit DACs in 10-Lead microSOICCHARACTERISTICS6Minimum Output Voltage 0.001 V This is a measure of the minimum and maximum drive6M ..
AD5314BRM-REEL7 , 2.5 V to 5.5 V, 500 μA, Quad Voltage Output 8-/10-/12-Bit DACs in 10-Lead Packages
AD5314BRM-REEL7 , 2.5 V to 5.5 V, 500 μA, Quad Voltage Output 8-/10-/12-Bit DACs in 10-Lead Packages
AD5315BRM ,2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACsCHARACTERISTICS6Minimum Output Voltage 0.001 V This is a measure of the minimum and maximum drive6M ..
AD5316ARU ,2.5 V to 5.5 V, 400 µA, 2-Wire Interface Quad Voltage Output 10-Bit DACGENERAL DESCRIPTIONLow Power Operation: 400 A @ 3 V, 500 A @ 5 VThe AD5306/AD5316/AD5326 are quad ..
AD9224ARS ,Complete 12-Bit 40 MSPS Monolithic A/D ConverterFEATURESMonolithic 12-Bit, 40 MSPS A/D ConverterAVDD DRVDDCLKLow Power Dissipation: 415 mWSHASingle ..
AD9225AR ,Complete 12-Bit, 25 MSPS Monolithic A/D ConverterFEATURESMonolithic 12-Bit, 25 MSPS A/D ConverterCLK AVDD DRVDDLow Power Dissipation: 280 mWSingle + ..
AD9225ARS ,Complete 12-Bit, 25 MSPS Monolithic A/D ConverterSPECIFICATIONS (AVDD = +5 V, DRVDD = +5 V, f = 25 MSPS, VREF = 2.0 V, VINB = 2.5 V dc, T to T unles ..
AD9226 ,12-Bit, 65 MSPS Analog-to-Digital ConverterFEATURES FUNCTIONAL BLOCK DIAGRAMSignal-to-Noise Ratio: 69 dB @ f = 31 MHzINDRVDDCLK AVDDSpurious-F ..
AD9226ARS ,Complete 12-Bit, 65 MSPS ADC ConverterSPECIFICATIONS noted.)Parameter Temp Test Level Min Typ Max UnitRESOLUTION 12 BitsACCURACYIntegral ..
AD9226ARS ,Complete 12-Bit, 65 MSPS ADC ConverterSPECIFICATIONS SAMPLE MIN MAXParameters Temp Test Level Min Typ Max Unit1 1 LOGIC INPUTS (Clock, DF ..

AD5313BRU-AD5323BRU
+2.5 V to +5.5 V, 230 uA, Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACs
REV.0
+2.5 V to +5.5 V, 230 �A, Dual Rail-to-Rail
Voltage Output 8-/10-/12-Bit DACs
FUNCTIONAL BLOCK DIAGRAM
VOUTA
VOUTB
VDDVREFA
VREFB
SYNC
SCLK
DIN
GND
BUF A
SDO
CLRBUF B
DCENLDAC
FEATURES
AD5303: Two Buffered 8-Bit DACs in One Package
AD5313: Two Buffered 10-Bit DACs in One Package
AD5323: Two Buffered 12-Bit DACs in One Package
16-Lead TSSOP Package
Micropower Operation: 300 �A @ 5 V (Including
Reference Current)
Power-Down to 200 nA @ 5 V, 50 nA @ 3 V
+2.5 V to +5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic By Design Over All Codes
Buffered/Unbuffered Reference Input Options
Output Range: 0–VREF or 0–2 VREF
Power-On-Reset to Zero Volts
SDO Daisy-Chaining Option
Simultaneous Update of DAC Outputs via LDAC Pin
Asynchronous CLR Facility
Low Power Serial Interface with Schmitt-Triggered
Inputs
On-Chip Rail-to-Rail Output Buffer Amplifiers
APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
GENERAL DESCRIPTION
The AD5303/AD5313/AD5323 are dual 8-, 10- and 12-bit
buffered voltage output DACs in a 16-lead TSSOP package that
operate from a single +2.5 V to +5.5 V supply consuming 230 µA
at 3 V. Their on-chip output amplifiers allow the outputs to
swing rail-to-rail with a slew rate of 0.7 V/µs. The AD5303/
AD5313/AD5323 utilize a versatile 3-wire serial interface that
operates at clock rates up to 30 MHz and is compatible with
standard SPI™, QSPI, MICROWIRE™ and DSP interface
standards.
The references for the two DACs are derived from two reference
pins (one per DAC). These reference inputs may be configured
as buffered or unbuffered inputs. The parts incorporate a power-
on-reset circuit that ensures that the DAC outputs power-up to
0 V and remain there until a valid write to the device takes place.
There is also an asynchronous active low CLR pin that clears
both DACs to 0 V. The outputs of both DACs may be updated
simultaneously using the asynchronous LDAC input. The
parts contain a power-down feature that reduces the current
consumption of the devices to 200 nA at 5 V (50 nA at 3 V) and
provides software-selectable output loads while in power-down
mode. The parts may also be used in daisy-chaining applications
using the SDO pin.
The low power consumption of these parts in normal operation
make them ideally suited to portable battery operated equip-
ment. The power consumption is 1.5 mW at 5 V, 0.7 mW at
3 V, reducing to 1 µW in power-down mode.
*. Patent No. 5684481; other patents pending.
SPI is a trademark of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
AD5303/AD5313/AD5323–SPECIFICATIONS
(VDD = +2.5 V to +5.5 V; VREF = +2 V; RL = 2 k� to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless otherwise noted.)
DC PERFORMANCE
OUTPUT CHARACTERISTICS
LOGIC INPUTS
LOGIC OUTPUT (SDO)
POWER REQUIREMENTS
AD5303/AD5313/AD5323
AC CHARACTERISTICS1(VDD = +2.5 V to +5.5 V; RL = 2 k� to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless
otherwise noted.)
Slew Rate
Major-Code Transition Glitch Energy
Digital Feedthrough
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
NOTESGuaranteed by design and characterization, not production tested.See Terminology.Temperature range: B Version: –40°C to +105°C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2, 3
NOTES
1Guaranteed by design and characterization, not production tested.
2All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3See Figures 1 and 2.
4These are measured with the load circuit of Figure 1.
5Daisy-Chain Mode only (see Figure 45).
Specifications subject to change without notice.
(VDD = +2.5 V to +5.5 V; all specifications TMIN to TMAX unless otherwise noted.)
NOTES
1See Terminology.
2Temperature range: B Version: –40°C to +105°C.
3DC specifications tested with the outputs unloaded.
4Linearity is tested using a reduced code range: AD5303 (Code 8 to 248); AD5313 (Code 28 to 995); AD5323 (Code 115 to 3981).
5Guaranteed by design and characterization, not production tested.
6In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, VREF =
VDD and “Offset plus Gain” Error must be positive.
Specifications subject to change without notice.
AD5303/AD5313/AD5323
Figure 1.Load Circuit for Digital Output (SDO) Timing Specifications
Figure 2.Serial Interface Timing Diagram
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5303/AD5313/AD5323 features proprietary ESD protection circuitry, perma-
nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
Digital Input Voltage to GND . . . . . . .–0.3 V to VDD + 0.3 V
Digital Output Voltage to GND . . . . .–0.3 V to VDD + 0.3 V
Reference Input Voltage to GND . . . .–0.3 V to VDD + 0.3 V
VOUTA, VOUTB to GND . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . .–40°C to +105°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature (TJ Max) . . . . . . . . . . . . . . . . .+150°C
16-Lead TSSOP Package
Power Dissipation . . . . . . . . . . . . . . . . . .(TJ Max – TA)/θJA
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .160°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
PIN CONFIGURATION
ORDERING GUIDE
AD5303/AD5313/AD5323
PIN FUNCTION DESCRIPTIONS
3VDD
4VREFB
5VREFA
TERMINOLOGY
RELATIVE ACCURACY
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the actual endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure 5.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified DNL of ±1 LSB maximum ensures
monotonicity. This DAC is guaranteed monotonic by design. A
OFFSET ERROR
This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.
GAIN ERROR
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.
OFFSET ERROR DRIFT
This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
MAJOR-CODE TRANSITION GLITCH ENERGY
Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC regis-
ter changes state. It is normally specified as the area of the glitch
in nV-secs and is measured when the digital code is changed by
1 LSB at the major carry transition (011...11 to 100...00 or
100...00 to 011...11).
DIGITAL FEEDTHROUGH
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital input pins of the
device, but is measured when the DAC is not being written to
(SYNC held high). It is specified in nV secs and is measured
with a full-scale change on the digital input pins, i.e., from all 0s
to all 1s and vice versa.
ANALOG CROSSTALK
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of the other DAC. It is measured
by loading one of the input registers with a full-scale code
change (all 0s to all 1s and vice versa) while keeping LDAC
high. Then pulse LDAC low and monitor the output of the
DAC whose digital code was not changed. The area of the glitch
is expressed in nV-secs.
DAC-TO-DAC CROSSTALK
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
the other DAC. This includes both digital and analog crosstalk.
It is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) while keeping LDAC low
and monitoring the output of the other DAC. The area of the
glitch is expressed in nV-secs.
DC CROSSTALK
This is the dc change in the output level of one DAC in re-
sponse to a change in the output of the other DAC. It is mea-
sured with a full-scale output change on one DAC while
monitoring the other DAC. It is expressed in µV.
POWER SUPPLY REJECTION RATIO (PSRR)
This indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change in
VOUT to a change in VDD for full-scale output of the DAC. It is
measured in dBs. VREF is held at +2 V and VDD is varied ±10%.
REFERENCE FEEDTHROUGH
This is the ratio of the amplitude of the signal at the DAC out-
put to the reference input when the DAC output is not being
updated (i.e., LDAC is high). It is expressed in dBs.
TOTAL HARMONIC DISTORTION
This is the difference between an ideal sine wave and its attenu-
ated version using the DAC. The sine wave is used as the refer-
ence for the DAC and the THD is a measure of the harmonics
present on the DAC output. It is measured in dBs.
MULTIPLYING BANDWIDTH
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
CHANNEL-TO-CHANNEL ISOLATION
This is a ratio of the amplitude of the signal at the output of one
DAC to a sine wave on the reference input of the other DAC. It
is measured in dBs.
Figure 3.Transfer Function with Negative Offset
Figure 4.Transfer Function with Positive Offset
AD5303/AD5313/AD5323
–Typical Performance Characteristics

Figure 5.AD5303 Typical INL Plot

Figure 8.AD5303 Typical DNL Plot
Figure 11.AD5303 INL and DNL Error
vs. VREF
Figure 6.AD5313 Typical INL Plot
CODE
DNL ERROR
LSBs
2000
Figure 9.AD5313 Typical DNL Plot
Figure 12.AD5303 INL Error and DNL
Error vs. Temperature

Figure 7.AD5323 Typical INL Plot
CODE
DNL ERROR
LSBs
–0.5
Figure 10.AD5323 Typical DNL Plot

TEMPERATURE – �C
ERROR
0.5
Figure 13.Offset Error and Gain
Error vs. Temperature

Figure 14.IDD Histogram with VDD =
+3 V and VDD = +5 V

VDD – Volts
400
Figure 17.Supply Current vs. Supply
Voltage

Figure 20.Half-Scale Settling (1/4 to
3/4 Scale Code Change)

Figure 15.Source and Sink Current
Capability

Figure 18.Power-Down Current vs.
Supply Voltage

Figure 21.Power-On Reset to 0 V
Figure 16.Supply Current vs. Code
Figure 19.Supply Current vs. Logic
Input Voltage

Figure 22.Exiting Power-Down to
Midscale

Partno	Mfg	Dc	Qty	Available	Descript
AD5313BRU	AD	N/a	21	avai	+2.5 V to +5.5 V, 230 uA, Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACs
AD5323BRU	AD	N/a	10	avai	+2.5 V to +5.5 V, 230 uA, Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACs