AD5308ARU-AD5328ARU Fast Delivery |IC PHOENIX CO.,LIMITED

AD5328ARU ,Octal 12-Bit Low Voltage Low Power Serial Vout DAC in 16 lead TSSOPGENERAL DESCRIPTIONA Version: 4 LSB INL, B Version: 3 LSB INLThe AD5308/AD5318/AD5328 are octal 8 ..
AD5328BRU , 2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
AD5328BRUZ-REEL7 , 2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
AD532JD ,Internally Trimmed Integrated Circuit MultiplierSPECIFICATIONS AD532J AD532K AD532SModel Min Typ Max Min Typ Max Min Typ Max UnitsMULTIPLIER PERFO ..
AD532JD/+ ,Internally Trimmed Integrated Circuit MultiplierSPECIFICATIONS S OS AD532J AD532K AD532SModel Min Typ Max Min Typ Max Min Typ Max UnitMULTIPLIER P ..
AD532JH ,Internally Trimmed Integrated Circuit Multiplierspecifications are guaranteed, although only those shownD-14: q = 22

AD5308ARU-AD5328ARU
Octal 8-Bit Low Voltage Low Power Serial Vout DAC in 16 lead TSSOP
REV.B
2.5 V to 5.5 V Octal Voltage Output
8-/10-/12-Bit DACs in 16-Lead TSSOP
*.Patent No. 5,969,657; other patents pending.
FEATURES
AD5308: 8 Buffered 8-Bit DACs in 16-Lead TSSOP
A Version: �1 LSB INL, B Version: �0.75 LSB INL
AD5318: 8 Buffered 10-Bit DACs in 16-Lead TSSOP
A Version: �4 LSB INL, B Version: �3 LSB INL
AD5328: 8 Buffered 12-Bit DACs in 16-Lead TSSOP
A Version: �16 LSB INL, B Version: �12 LSB INL
Low Power Operation: 0.7 mA @ 3 V
Guaranteed Monotonic by Design over All Codes
Power-Down to 120 nA @ 3 V, 400 nA @ 5 V
Double-Buffered Input Logic
Buffered/Unbuffered/VDD Reference Input Options
Output Range: 0 V to VREF or 0 V to 2 VREF
Power-On Reset to 0 V
Programmability
Individual Channel Power-Down
Simultaneous Update of Outputs (LDAC)
Low Power, SPI®, QSPI™, MICROWIRE™, and DSP
Compatible 3-Wire Serial Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range –40�C to +105�C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Optical Networking
Automatic Test Equipment
FUNCTIONAL BLOCK DIAGRAM
DIN
GND
VOUTB
VOUTC
VOUTD
VOUTE
VOUTG
VOUTH
VOUTF
VDD
VOUTA
VREFEFGH
VREFABCD
SYNC
SCLK
LDAC
GENERAL DESCRIPTION
The AD5308/AD5318/AD5328 are octal 8-, 10-, and 12-bit
buffered voltage output DACs in a 16-lead TSSOP. They operate
from a single 2.5 V to 5.5 V supply, consuming 0.7 mA typ at 3 V.
Their on-chip output amplifiers allow the outputs to swing
rail-to-rail with a slew rate of 0.7 V/µs. The AD5308/AD5318/
AD5328 use a versatile 3-wire serial interface that operates at
clock rates up to 30 MHz and is compatible with standard
SPI, QSPI, MICROWIRE, and DSP interface standards.
The references for the eight DACs are derived from two reference
pins (one per DAC quad). These reference inputs can be
configured as buffered, unbuffered, or VDD inputs. The parts
incorporate a power-on reset circuit, which ensures that the DAC
outputs power up to 0 V and remain there until a valid write to
the device takes place. The outputs of all DACs may be updated
simultaneously using the asynchronous LDAC input. The parts
contain a power-down feature that reduces the current consump-
tion of the devices to 400 nA at 5 V (120 nA at 3 V). The eight
channels of the DAC may be powered down individually.
All three parts are offered in the same pinout, which allows
users to select the resolution appropriate for their application
without redesigning their circuit board.
Mobile Communications
Programmable Attenuators
Industrial Process Control
AD5308/AD5318/AD5328–SPECIFICATIONS(VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 k� to
GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.)
DC PERFORMANCE
OUTPUT CHARACTERISTICS6
POWER REQUIREMENTS
NOTESSee the Terminology section.Temperature range (A, B Version): –40°C to +105°C; typical at +25°C.DC specifications tested with the outputs unloaded unless stated otherwise.Linearity is tested using a reduced code range: AD5308 (Code 8 to Code 255), AD5318 (Code 28 to Code 1023), and AD5328 (Code 115 to Code 4095).This corresponds to x codes. x = deadband voltage/LSB size.Guaranteed by design and characterization; not production tested.
AD5308/AD5318/AD5328
AC CHARACTERISTICS1(VDD = 2.5 V to 5.5 V; RL = 2 k� to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless
otherwise noted.)
Slew Rate
NOTESGuaranteed by design and characterization; not production tested.See the Terminology section.Temperature range (A, B Version): –40°C to +105°C; typical at +25°C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2, 3
NOTESGuaranteed by design and characterization; not production tested.All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.See Figures 2 and 3.
Specifications subject to change without notice.
AD5308/AD5318/AD5328
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = 25°C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . –0.3 V to VDD + 0.3 V
Reference Input Voltage to GND . . . . –0.3 V to VDD + 0.3 V
VOUTA–VOUTD to GND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (A, B Version) . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ MAX) . . . . . . . . . . . . . . . . . . . 150°C
ORDERING GUIDE
AD5308ARU-REEL7
AD5308BRU
AD5308BRU-REEL
AD5308BRU-REEL7
AD5318ARU
AD5318ARU-REEL7
AD5318BRU
AD5318BRU-REEL
AD5318BRU-REEL7
AD5318BRUZ*
AD5318BRUZ-REEL*
AD5318BRUZ-REEL7*
AD5328ARU
AD5328ARU-REEL7
AD5328BRU
AD5328BRU-REEL
*Z = Pb-free part.
16-Lead TSSOP
Power Dissipation . . . . . . . . . . . . . . . . . . . (TJ MAX – TA)/�JA
�JA Thermal Impedance . . . . . . . . . . . . . . . . . . . 150.4°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5308/AD5318/AD5328 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
3VDD
4VOUTABuffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
5VOUTBBuffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
6VOUTCBuffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
7VOUTDBuffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
8VREFABCD
AD5308/AD5318/AD5328
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSB, from a straight
line passing through the endpoints of the DAC transfer function.
Typical INL versus code plots can be seen in TPCs 1, 2, and 3.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. Typical DNL versus code plots can be
seen in TPCs 4, 5, and 6.
Offset Error
This is a measure of the offset error of the DAC and the output
amplifier (see Figures 2 and 3). It can be negative or positive,
and is expressed in mV.
Gain Error
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.
Offset Error Drift
This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
DC Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT
to a change in VDD for full-scale output of the DAC. It is mea-
sured in dB. VREF is held at 2 V and VDD is varied ±10%.
DC Crosstalk
This is the dc change in the output level of one DAC in response
to a change in the output of another DAC. It is measured with a
full-scale output change on one DAC while monitoring another
DAC. It is expressed in µV.
Reference Feedthrough
This is the ratio of the amplitude of the signal at the DAC out-
put to the reference input when the DAC output is not being
updated (i.e., LDAC is high). It is expressed in dB.
Channel-to-Channel Isolation
This is the ratio of the amplitude of the signal at the output of
one DAC to a sine wave on the reference input of another DAC.
It is measured in dB.
Major-Code Transition Glitch Energy
Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC
register changes state. It is normally specified as the area of the
glitch in nV-s and is measured when the digital code is changed by
1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or
100 . . . 00 to 011 . . . 11).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of a DAC from the digital input pins of the device,
but is measured when the DAC is not being written to (SYNC
held high). It is specified in nV-s and is measured with a full-
scale change on the digital input pins, i.e., from all 0s to all 1s
and vice versa.
Digital Crosstalk
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nV-s.
Analog Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured
by loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa) while keeping LDAC high. Then
pulse LDAC low and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-s.
DAC-to-DAC Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk. It
is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with LDAC low and
monitoring the output of another DAC. The energy of the glitch
is expressed in nV-s.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Total Harmonic Distortion
This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC, and the THD is a measure of the harmonics present
on the DAC output. It is measured in dB.
Figure 2. Transfer Function with Negative Offset
(VREF = VDD)
Figure 3. Transfer Function with Positive Offset
AD5308/AD5318/AD5328–Typical Performance Characteristics
TPC 1.AD5308 Typical INL Plot
TPC 4.AD5308 Typical DNL Plot
TPC 7.AD5308 INL and DNL
Error vs. VREF
TPC 2.AD5318 Typical INL Plot
CODE
DNL ERROR (LSB)
2000
TPC 5.AD5318 Typical DNL Plot
TEMPERATURE (�C)
ERROR (LSB)
–0.5�40040
0.4
TPC 8.AD5308 INL Error and
DNL Error vs. Temperature
TPC 3.AD5328 Typical INL Plot
CODE
DNL ERROR (LSB)
10000
TPC 6.AD5328 Typical DNL Plot
TPC 9.AD5308 Offset Error and
Gain Error vs. Temperature
TPC 10.Offset Error and
Gain Error vs. VDD
TPC 13.Supply Current vs.
Supply Voltage
TPC 16.Half-Scale Settling (1/4
to 3/4 Scale Code Change)
TPC 11.VOUT Source and
Sink Current Capability
TPC 14.Power-Down Current vs.
Supply Voltage
TPC 17.Power-On Reset to 0 V
TPC 12.Supply Current vs.
DAC Code
VLOGIC (V)
(mA)
1.52.53.50.54.55.0
TPC 15.Supply Current vs. Logic
Input Voltage for SCLK and DIN
Increasing and Decreasing
TPC 18.Exiting Power-Down
to Midscale
AD5308/AD5318/AD5328
TPC 19.IDD Histogram with
VDD = 3 V and VDD = 5 V
TPC 22.Full-Scale Error vs. VREF
TPC 20.AD5328 Major-Code
Transition Glitch Energy
TPC 23.DAC-to-DAC Crosstalk
TPC 21.Multiplying Bandwidth
(Small-Signal Frequency Response)

Partno	Mfg	Dc	Qty	Available	Descript
AD5308ARU	AD	N/a	13	avai	Octal 8-Bit Low Voltage Low Power Serial Vout DAC in 16 lead TSSOP
AD5328ARU	AD	N/a	300	avai	Octal 12-Bit Low Voltage Low Power Serial Vout DAC in 16 lead TSSOP