AD5305BRM-REEL-AD5305BRM-REEL7 Fast Delivery |IC PHOENIX CO.,LIMITED

AD5305BRM-REEL ,2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACsCHARACTERISTICS6Minimum Output Voltage 0.001 0.001 V This is a measure of the minimumand maximum dr ..
AD5305BRM-REEL7 ,2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACsGENERAL DESCRIPTIONAD5305: 4 Buffered 8-Bit DACs in 10-Lead MSOP The AD5305/AD5315/AD5325 are quad ..
AD5306BRU , 2.5 V to 5.5 V, 400 μA, 2-Wire Interface, Quad Voltage Output, 8-/10-/12-Bit DACs
AD5308ARU ,Octal 8-Bit Low Voltage Low Power Serial Vout DAC in 16 lead TSSOPspecifications T to T , unless otherwise noted.)L MIN MAX2 2A Version B Version1Parameter Min Typ M ..
AD5308ARUZ , 2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
AD5308ARUZ , 2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
AD9214BRS-65 ,10-Bit, 65/80/105 MSPS 3 V A/D ConverterAPPLICATIONSBattery-Powered InstrumentsAGND REF REFSENSE DGNDHand-Held ScopemetersLow-Cost Digital ..
AD9214BRS-65 ,10-Bit, 65/80/105 MSPS 3 V A/D ConverterFEATURES FUNCTIONAL BLOCK DIAGRAMSNR = 57 dB @ 39 MHz Analog Input (–0.5 dBFS)AV PWRDWN DrVLow Powe ..
AD9214BRS-80 ,10-Bit, 65/80/105 MSPS 3 V A/D ConverterSPECIFICATIONS frequency used, unless otherwise noted.)Test AD9214-65 AD9214-80 AD9214-105Parameter ..
AD9215BCP-105 ,10-Bit, 65/80/105 MSPS, 3V A/D ConverterFEATURES FUNCTIONAL BLOCK DIAGRAM AVDD DRVDDSingle 3 V supply operation (2.7 V to 3.3 V) SNR = 58 d ..
AD9215BCP-65 ,10-Bit, 65/80/105 MSPS, 3V A/D Converterapplications in communications, imag-4. The AD9215 is part of several pin compatible 10-, 12-, and ..
AD9215BCP-80 ,10-Bit, 65/80/105 MSPS, 3V A/D ConverterSpecifications 2 Applying the AD9215 Theory of Operation.... 14 Changes to Figure 2. 4 Clock Input ..

AD5305BRM-REEL-AD5305BRM-REEL7
2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
REV.F
2.5 V to 5.5 V, 500 �A, 2-Wire Interface
Quad Voltage Output, 8-/10-/12-Bit DACs
*.Patent No. 5,969,657and 5,684,481.
FEATURES
AD5305: 4 Buffered 8-Bit DACs in 10-Lead MSOP
A Version: �1 LSB INL, B Version: �0.625 LSB INL
AD5315: 4 Buffered 10-Bit DACs in 10-Lead MSOP
A Version: �4 LSB INL, B Version: �2.5 LSB INL
AD5325: 4 Buffered 12-Bit DACs in 10-Lead MSOP
A Version: �16 LSB INL, B Version: �10 LSB INL
Low Power Operation: 500 �A @ 3 V, 600 �A @ 5 V
2-Wire (I2C® Compatible) Serial Interface
2.5 V to 5.5 V Power Supply
Guaranteed Monotonic by Design over All Codes
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V
Three Power-Down Modes
Double-Buffered Input Logic
Output Range: 0 V to VREF
Power-On Reset to 0 V
Simultaneous Update of Outputs (LDAC Function)
Software Clear Facility
Data Readback Facility
On-Chip Rail-to-Rail Output Buffer Ampliﬁers
Temperature Range –40�C to +105�C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
FUNCTIONAL BLOCK DIAGRAMVOUTA
VDDREF IN
GNDVOUTBVOUTCVOUTD
SDA
SCL
GENERAL DESCRIPTION
The AD5305/AD5315/AD5325 are quad 8-, 10-, and 12-bit
buffered voltage output DACs in a 10-lead MSOP that operate
from a single 2.5 V to 5.5 V supply, consuming 500 µA at 3 V.
Their on-chip output ampliﬁers allow rail-to-rail output swing
with a slew rate of 0.7 V/µs. A 2-wire serial interface, which
operates at clock rates up to 400 kHz, is used. This interface is
SMBus compatible at VDD < 3.6 V. Multiple devices can be
placed on the same bus.
The references for the four DACs are derived from one reference
pin. The outputs of all DACs may be updated simultaneously
using the software LDAC function. The parts incorporate a
power-on reset circuit, which ensures that the DAC outputs power
up to 0 V and remain there until a valid write takes place to the
device. There is also a software clear function that resets all input
and DAC registers to 0 V. The parts contain a power-down
feature that reduces the current consumption of the devices to
200 nA @ 5 V (80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equipment.
The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, reducing
to 1 µW in power-down mode.
AD5305/AD5315/AD5325–SPECIFICATIONS(VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 k� to GND;
CL = 200 pF to GND; all speciﬁcations TMIN to TMAX, unless otherwise noted.)
OUTPUT CHARACTERISTICS
LOGIC INPUTS (A0)
LOGIC INPUTS (SCL, SDA)
LOGIC OUTPUT (SDA)
AD5305/AD5315/AD5325
AC CHARACTERISTICS1(VDD = 2.5 V to 5.5 V; RL = 2 k� to GND; CL = 200 pF to GND; all speciﬁcations TMIN to TMAX, unless
otherwise noted.)
NOTESSee the Terminology section.Temperature range (A, B Version): –40°C to +105°C; typical at +25°C.DC speciﬁcations tested with the outputs unloaded.Linearity is tested using a reduced code range: AD5305 (Code 8 to 248); AD5315 (Code 28 to 995); AD5325 (Code 115 to 3981).Guaranteed by design and characterization, not production tested.For the ampliﬁer output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, VREF = VDD and offset plus gain error must be
positive.IDD speciﬁcation is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.
Speciﬁcations subject to change without notice.
Output Voltage Settling Time
NOTESGuaranteed by design and characterization, not production tested.See the Terminology section.Temperature range (A, B Version): –40°C to +105°C; typical at +25°C.
Speciﬁcations subject to change without notice.
AD5305/AD5315/AD5325
TIMING CHARACTERISTICS1, 2 (VDD = 2.5 V to 5.5 V; all speciﬁcations TMIN to TMAX, unless otherwise noted.)
t10
NOTESSee Figure 1.Guaranteed by design and characterization; not production tested.A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH min of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.
Specifications subject to change without notice.
Figure 1. 2-Wire Serial Interface Timing Diagram
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5305/AD5315/AD5325 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = 25°C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
SCL, SDA to GND . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
A0 to GND . . . . . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Reference Input Voltage to GND . . . . .–0.3 V to VDD + 0.3 V
VOUTA–D to GND . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (A, B Version) . . . . . . . . . . . . . .–40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . .150°C
MSOP
Power Dissipation . . . . . . . . . . . . . . . . . . .(TJ max – TA)/�JA
�JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .206°C/W
�JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .44°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . .220°C
Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this speciﬁcation is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
AD5305/AD5315/AD5325
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
3VOUTBBuffered Analog Output Voltage from DAC B. The output ampliﬁer has rail-to-rail operation.
4VOUTCBuffered Analog Output Voltage from DAC C. The output ampliﬁer has rail-to-rail operation.
7GND
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSB, from a straight
line passing through the endpoints of the DAC transfer function.
Typical INL versus code plots can be seen in TPCs 1, 2, and 3.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A speciﬁed differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. Typical DNL versus code plots can be
seen in TPCs 4, 5, and 6.
Offset Error
This is a measure of the offset error of the DAC and the output
ampliﬁer. It is expressed as a percentage of the full-scale range.
Gain Error
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.
Offset Error Drift
This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in dB. VREF is held at 2 V and VDD is varied ±10%.
DC Crosstalk
This is the dc change in the output level of one DAC at midscale
in response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of another DAC. It is expressed in µV.
Reference Feedthrough
This is the ratio of the amplitude of the signal at the DAC out-
put to the reference input when the DAC output is not being
updated. It is expressed in dB.
Major-Code Transition Glitch Energy
Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC
register changes state. It is normally speciﬁed as the area of the
glitch in nV-s and is measured when the digital code is changed by
1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00,
or 100 . . . 00 to 011 . . . 11).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital input pins of the
device when the DAC output is not being updated. It is speciﬁed
in nV-s and is measured with a worst-case change on the
digital input pins, e.g., from all 0s to all 1s or vice versa.
Digital Crosstalk
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
expressed in nV-s.
DAC-to-DAC Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk. It
is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with the LDAC bit set
low and monitoring the output of another DAC. The energy of
the glitch is expressed in nV-s.
Multiplying Bandwidth
The ampliﬁers within the DAC have a ﬁnite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Total Harmonic Distortion
This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference for
the DAC and the THD is a measure of the harmonics present
on the DAC output. It is measured in dB.
Figure 2. Transfer Function with Negative Offset
Figure 3. Transfer Function with Positive Offset
AD5305/AD5315/AD5325–Typical Performance Characteristics
TPC 1.AD5305 Typical INL Plot
CODE
DNL ERROR (LSB)
0.1
TPC 4.AD5305 Typical DNL Plot
TPC 7.AD5305 INL and DNL
Error vs. VREF
CODE
INL ERROR (LSB)2001000400600800
TPC 2.AD5315 Typical INL Plot
TPC 5.AD5315 Typical DNL Plot
TEMPERATURE (�C)
ERROR (LSB)
–0.5�40040
0.4
TPC 8.AD5305 INL and DNL
Error vs. Temperature
TPC 3.AD5325 Typical INL Plot
CODE
DNL ERROR (LSB)
10000
TPC 6.AD5325 Typical DNL Plot
TEMPERATURE (�C)
ERROR (%)
–1.0�40040
–0.5120
TPC 9.AD5305 Offset Error and
Gain Error vs. Temperature
VDD (V)
ERROR (%)
0.1
TPC 10.Offset Error and
Gain Error vs. VDD
VDD (V)
2.53.04.04.55.53.55.0
TPC 13.Supply Current vs.
Supply Voltage
TPC 16.Half-Scale Settling (1/4 to
3/4 Scale Code Change)
TPC 11.VOUT Source and
Sink Current Capability
VDD (V)
2.53.04.04.55.53.55.0
TPC 14.Power-Down Current
vs. Supply Voltage
TPC 17.Power-On Reset to 0 V
TPC 12.Supply Current vs.
DAC Code
TPC 15.Supply Current vs. Logic
Input Voltage for SDA and SCL
Voltage Increasing and Decreasing
TPC 18.Exiting Power-Down
to Midscale
AD5305/AD5315/AD5325
FUNCTIONAL DESCRIPTION
The AD5305/AD5315/AD5325 are quad resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10, and 12
bits, respectively. Each contains four output buffer ampliﬁers
and is written to via a 2-wire serial interface. They operate from
single supplies of 2.5 V to 5.5 V, and the output buffer ampliﬁers
provide rail-to-rail output swing with a slew rate of 0.7 V/µs.
The four DACs share a single reference input pin. The devices
have three programmable power-down modes, in which all
DACs may be turned off completely with a high impedance
output, or the outputs may be pulled low by on-chip resistors.
Digital-to-Analog Section
The architecture of one DAC channel consists of a resistor-string
DAC followed by an output buffer ampliﬁer. The voltage at the
REFIN pin provides the reference voltage for the DAC. Figure 4
shows a block diagram of the DAC architecture. Since the input
coding to the DAC is straight binary, the ideal output voltage is
given by
TPC 19. IDD Histogram with
VDD = 3 V and VDD = 5 V
VREF (V)
FULL-SCALE ERROR (V)
–0.01
TPC 22. Full-Scale Error vs. VREF
TPC 20. AD5325 Major-Code
Transition Glitch Energy
TPC 23. DAC-to-DAC Crosstalk
TPC 21. Multiplying Bandwidth
(Small-Signal Frequency Response)
where
D = decimal equivalent of the binary code, which is loaded to
the DAC register:
0–255 for AD5305 (8 bits)
0–1023 for AD5315 (10 bits)
0–4095 for AD5325 (12 bits)
N = DAC resolution
Figure 4. DAC Channel Architecture

Partno	Mfg	Dc	Qty	Available	Descript
AD5305BRM-REEL \|AD5305BRMREEL	AD	N/a	3146	avai	2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
AD5305BRM-REEL7 \|AD5305BRMREEL7	AD	N/a	514	avai	2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs