AD5305BRM-AD5315BRM-AD5325BRM Fast Delivery |IC PHOENIX CO.,LIMITED

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AD5305BRM-AD5315BRM-AD5325BRM
2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
REV.B
2.5 V to 5.5 V, 500 �A, 2-Wire Interface
Quad Voltage Output, 8-/10-/12-Bit DACs
FUNCTIONAL BLOCK DIAGRAMVOUTA
VDDREF IN
GNDVOUTBVOUTCVOUTD
SDA
SCL
FEATURES
AD5305
Four Buffered 8-Bit DACs in 10-Lead microSOIC
AD5315
Four Buffered 10-Bit DACs in 10-Lead microSOIC
AD5325
Four Buffered 12-Bit DACs in 10-Lead microSOIC
Low Power Operation: 500 �A @ 3 V, 600 �A @ 5 V
2-Wire (I2C®-Compatible) Serial Interface
2.5 V to 5.5 V Power Supply
Guaranteed Monotonic By Design Over All Codes
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V
Double-Buffered Input Logic
Output Range: 0–VREF
Power-On-Reset to Zero Volts
Simultaneous Update of Outputs (LDAC Function)
Software Clear Facility
Data Readback Facility
On-Chip Rail-to-Rail Output Buffer Ampliﬁers
Temperature Range –40�C to +105�C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
GENERAL DESCRIPTION
The AD5305/AD5315/AD5325 are quad 8-, 10- and 12-bit
buffered voltage output DACs in a 10-lead microSOIC package
that operate from a single 2.5 V to 5.5 V supply consuming
500 µA at 3 V. Their on-chip output ampliﬁers allow rail-to-rail
output swing with a slew rate of 0.7 V/µs. A 2-wire serial inter-
face is used which operates at clock rates up to 400 kHz. This
interface is SMBus-compatible at VDD < 3.6 V. Multiple devices
can be placed on the same bus.
The references for the four DACs are derived from one reference
pin. The outputs of all DACs may be updated simultaneously
using the software LDAC function. The parts incorporate a
power-on-reset circuit that ensures that the DAC outputs power
up to zero volts and remain there until a valid write takes place
to the device. There is also a software clear function which resets
all input and DAC registers to 0 V. The parts contain a power-
down feature that reduces the current consumption of the devices
to 200 nA @ 5 V (80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equip-
ment. The power consumption is 3 mW at 5 V, 1.5 mW at 3 V,
reducing to 1 µW in power-down mode.
*. Patent No. 5,969,657; other patents pending.2C is a registered trademark of Philips Corporation.
AD5305/AD5315/AD5325–SPECIFICATIONS(VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 k� to
GND; CL = 200 pF to GND; All speciﬁcations TMIN to TMAX unless otherwise noted.)
OUTPUT CHARACTERISTICS
LOGIC INPUTS (A0)
LOGIC INPUTS (SCL, SDA)
LOGIC OUTPUT (SDA)
POWER REQUIREMENTS
AD5305/AD5315/AD5325
AC CHARACTERISTICS1(VDD = 2.5 V to 5.5 V; RL = 2 k� to GND; CL = 200 pF to GND; all speciﬁcations TMIN to TMAX unless
otherwise noted.)
NOTES
1Guaranteed by design and characterization, not production tested.
2See Terminology.
3Temperature range: B Version: –40°C to +105°C; typical at 25°C.
Speciﬁcations subject to change without notice.
TIMING CHARACTERISTICS1, 2
NOTESSee Figure 1.Guaranteed by design and characterization, not production tested.CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.
Speciﬁcations subject to change without notice.
NOTESSee Terminology.Temperature range: B Version: –40°C to +105°C; typical at 25°C.DC speciﬁcations tested with the outputs unloaded.Linearity is tested using a reduced code range: AD5305 (Code 8 to 248); AD5315 (Code 28 to 995); AD5325 (Code 115 to 3981).Guaranteed by design and characterization, not production tested.For the ampliﬁer output to reach its minimum voltage, Offset Error must be negative; to reach its maximum voltage, VREF = VDD and “Offset plus Gain” Error must be positive.IDD speciﬁcation is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.
Speciﬁcations subject to change without notice.
(VDD = 2.5 V to 5.5 V. All speciﬁcations TMIN to TMAX unless otherwise noted)
AD5305/AD5315/AD5325
Figure 1.Two-Wire Serial Interface Timing Diagram
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = 25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
SCL, SDA to GND . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
A0 to GND . . . . . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Reference Input Voltage to GND . . . .–0.3 V to VDD + 0.3 V
VOUTA–D to GND . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . .–40°C to +105°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . .150°C
microSOIC Package
Power Dissipation . . . . . . . . . . . . . . . . . .(TJ max – TA)/θJA
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .206°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . .44°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . .220 +5/–0°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; and functional operation
of the device at these or any other conditions above those listed in the operational
sections of this speciﬁcation is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5305/AD5315/AD5325 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
TERMINOLOGY
RELATIVE ACCURACY
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
Typical INL versus Code plots can be seen in Figures 4, 5, and 6.
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A speciﬁed differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed mono-
tonic by design. Typical DNL versus Code plots can be seen in
Figures 7, 8, and 9.
OFFSET ERROR
This is a measure of the offset error of the DAC and the output
ampliﬁer. It is expressed as a percentage of the full-scale range.
GAIN ERROR
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.
OFFSET ERROR DRIFT
This is a measure of the change in offset error with changes
in temperature. It is expressed in (ppm of full-scale range)/°C.
GAIN ERROR DRIFT
This is a measure of the change in gain error with changes
in temperature. It is expressed in (ppm of full-scale range)/°C.
POWER-SUPPLY REJECTION RATIO (PSRR)
This indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change
in VOUT to a change in VDD for full-scale output of the DAC. It is
measured in dBs. VREF is held at 2 V and VDD is varied ±10%.
DC CROSSTALK
This is the dc change in the output level of one DAC at mid-
scale in response to a full-scale code change (all 0s to all 1s
and vice versa) and output change of another DAC. It is
expressed in µV.
REFERENCE FEEDTHROUGH
This is the ratio of the amplitude of the signal at the DAC
output to the reference input when the DAC output is not
being updated. It is expressed in dBs.
AD5305/AD5315/AD5325
MAJOR-CODE TRANSITION GLITCH ENERGY
Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC
register changes state. It is normally speciﬁed as the area of the
glitch in nV-secs and is measured when the digital code is changed
by 1 LSB at the major carry transition (011...11 to 100...00
or 100...00 to 011...11).
DIGITAL FEEDTHROUGH
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital input pins of the
device when the DAC output is not being updated. It is speciﬁed
in nV-secs and is measured with a worst-case change on the
digital input pins, e.g., from all 0s to all 1s or vice versa.
DIGITAL CROSSTALK
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
expressed in nV-secs.
DAC-TO-DAC CROSSTALK
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk. It
is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with the LDAC bit set low
and monitoring the output of another DAC. The energy of the
glitch is expressed in nV-secs.
MULTIPLYING BANDWIDTH
The ampliﬁers within the DAC have a ﬁnite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at which
the output amplitude falls to 3 dB below the input.
TOTAL HARMONIC DISTORTION
This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC and the THD is a measure of the harmonics present
on the DAC output. It is measured in dBs.
Figure 2.Transfer Function with Negative Offset
Figure 3.Transfer Function with Positive Offset
Figure 4.AD5305 Typical INL Plot
Figure 7.AD5305 Typical DNL Plot
Figure 10.AD5305 INL and DNL
Error vs. VREF
CODE
INL ERROR
LSBs2001000400600800
Figure 5.AD5315 Typical INL Plot
CODE
DNL ERROR
LSBs
2000
Figure 8.AD5315 Typical DNL Plot
TEMPERATURE – �C
ERROR
LSBs
–0.5�40040
0.4
Figure 11.AD5305 INL Error and
DNL Error vs. Temperature
CODE
INL ERROR
LSBs4000100020003000
–12
Figure 6.AD5325 Typical INL Plot
CODE
DNL ERROR
LSBs
10000
Figure 9.AD5325 Typical DNL Plot
TEMPERATURE – �C
ERROR
0.5�40040
–0.5120
Figure 12.AD5305 Offset Error and
Gain Error vs. Temperature
AD5305/AD5315/AD5325
VDD – Volts
ERROR
0.1
Figure 13.Offset Error and Gain
Error vs. VDD
VDD – Volts
2.53.04.04.55.53.55.0
Figure 16.Supply Current vs. Supply
Voltage
Figure 19.Half-Scale Settling (1/4 to
3/4 Scale Code Change)
Figure 14.VOUT Source and Sink
Current Capability
VDD – Volts
2.53.04.04.55.53.55.0
Figure 17.Power-Down Current vs.
Supply Voltage
Figure 20.Power-On Reset to 0 V
Figure 15.Supply Current vs. DAC
Code
VLOGIC – Volts
IDD
1.02.03.04.05.0
Figure 18.Supply Current vs. Logic
Input Voltage for SDA and SCL Volt-
age Increasing and Decreasing
Figure 21.Exiting Power-Down to
Midscale
Figure 22.IDD Histogram with
VDD = 3 V and VDD = 5 V
VREF – Volts
FULL-SCALE ERROR
Volts
–0.01
Figure 25.Full-Scale Error vs. VREF
Figure 23.AD5325 Major-Code
Transition Glitch Energy
Figure 26.DAC–DAC Crosstalk
FREQUENCY – kHz
0.11101001k10k
–60
Figure 24.Multiplying Bandwidth
(Small-Signal Frequency Response)
AD5305/AD5315/AD5325
FUNCTIONAL DESCRIPTION
The AD5305/AD5315/AD5325 are quad resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10, and 12
bits respectively. Each contains four output buffer ampliﬁers and
is written to via a 2-wire serial interface. They operate from
single supplies of 2.5 V to 5.5 V, and the output buffer ampliﬁers
provide rail-to-rail output swing with a slew rate of 0.7 V/µs. The
four DACs share a single reference input pin. The devices have
three programmable power-down modes, in which all DACs may
be turned off completely with a high-impedance output, or the
outputs may be pulled low by on-chip resistors.
Digital-to-Analog Section
The architecture of one DAC channel consists of a resistor-string
DAC followed by an output buffer ampliﬁer. The voltage at the
REFIN pin provides the reference voltage for the DAC. Figure
27 shows a block diagram of the DAC architecture. Since the
input coding to the DAC is straight binary, the ideal output volt-
age is given by:
where
D = decimal equivalent of the binary code, which is loaded to the
DAC register;
0–255 for AD5305 (8 Bits)
0–1023 for AD5315 (10 Bits)
0–4095 for AD5325 (12 Bits)
N = DAC resolution
Figure 27.DAC Channel Architecture
Resistor String
The resistor string section is shown in Figure 28. It is simply a
string of resistors, each of value R. The digital code loaded to the
DAC register determines at what node on the string the voltage
is tapped off to be fed into the output ampliﬁer. The voltage is
tapped off by closing one of the switches connecting the string to
the ampliﬁer. Because it is a string of resistors, it is guaranteed
monotonic.
DAC Reference Inputs
There is a single reference input pin for the four DACs. The
reference input is unbuffered. The user can have a reference
voltage as low as 0.25 V and as high as VDD since there is no
restriction due to headroom and footroom of any reference
ampliﬁer.
It is recommended to use a buffered reference in the external
circuit (e.g., REF192). The input impedance is typically 45 kΩ.
Output Ampliﬁer
The output buffer ampliﬁer is capable of generating rail-to-rail
voltages on its output, which gives an output range of 0 V to VDD
when the reference is VDD. It is capable of driving a load of
2 kΩ to GND or VDD, in parallel with 500 pF to GND or VDD.
The source and sink capabilities of the output ampliﬁer can be
seen in the plot in Figure 14.
The slew rate is 0.7 V/µs with a half-scale settling time to
±0.5 LSB (at 8 bits) of 6 µs.
POWER-ON RESET
The AD5305/AD5315/AD5325 are provided with a power-on
reset function, so that they power up in a deﬁned state. The
power-on state is:Normal operation.Output voltage set to 0 V.
Both input and DAC registers are ﬁlled with zeros and remain
so until a valid write sequence is made to the device. This is par-
ticularly useful in applications where it is important to know the
state of the DAC outputs while the device is powering up.
SERIAL INTERFACE
The AD5305/AD5315/AD5325 are controlled via an I2C-
compatible serial bus. The DACs are connected to this bus as
slave devices (i.e., no clock is generated by the AD5305/AD5315/
AD5325 DACs). This interface is SMBus-compatible at VDD
< 3.6 V.
The AD5305/AD5315/AD5325 have a 7-bit slave address. The
6 MSBs are 000110 and the LSB is determined by the state of
the A0 pin. The facility to make hardwired changes to A0 allows
the user to use up to two of these devices on one bus.
The 2-wire serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the SDA
line occurs while SCL is high. The following byte is the ad-
dress byte which consists of the 7-bit slave address followed
by a R/W bit (this bit determines whether data will be read
from or written to the slave device).
The slave whose address corresponds to the transmitted
address responds by pulling SDA low during the ninth clock
pulse (this is termed the acknowledge bit). At this stage, all
other devices on the bus remain idle while the selected device
waits for data to be written to or read from its shift register.Data is transmitted over the serial bus in sequences of nine
clock pulses (8-data bits followed by an acknowledge bit). The
transitions on the SDA line must occur during the low period

Partno	Mfg	Dc	Qty	Available	Descript
AD5305BRM	AD	N/a	9	avai	2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
AD5315BRM	AD	N/a	2	avai	2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
AD5325BRM	AD	N/a	372	avai	2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs