AD5304BRM-AD5314BRM-AD5324BRM Fast Delivery |IC PHOENIX CO.,LIMITED

AD5314BRM ,2.5 V to 5.5 V, 500 uA, Quad Voltage Output 8-/10-/12-Bit DACs in 10-Lead microSOICCHARACTERISTICS6Minimum Output Voltage 0.001 V This is a measure of the minimum and maximum drive6M ..
AD5314BRM-REEL7 , 2.5 V to 5.5 V, 500 μA, Quad Voltage Output 8-/10-/12-Bit DACs in 10-Lead Packages
AD5314BRM-REEL7 , 2.5 V to 5.5 V, 500 μA, Quad Voltage Output 8-/10-/12-Bit DACs in 10-Lead Packages
AD5315BRM ,2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACsCHARACTERISTICS6Minimum Output Voltage 0.001 V This is a measure of the minimum and maximum drive6M ..
AD5316ARU ,2.5 V to 5.5 V, 400 µA, 2-Wire Interface Quad Voltage Output 10-Bit DACGENERAL DESCRIPTIONLow Power Operation: 400 A @ 3 V, 500 A @ 5 VThe AD5306/AD5316/AD5326 are quad ..
AD5316BRU ,2.5 V to 5.5 V, 400 µA, 2-Wire Interface Quad Voltage Output 10-Bit DACSPECIFICATIONS (V = 2.5 V to 5.5 V; V = 2 V; R = 2 k toDD REF LGND; C = 200 pF to GND; all speciﬁc ..
AD9225AR ,Complete 12-Bit, 25 MSPS Monolithic A/D ConverterFEATURESMonolithic 12-Bit, 25 MSPS A/D ConverterCLK AVDD DRVDDLow Power Dissipation: 280 mWSingle + ..
AD9225ARS ,Complete 12-Bit, 25 MSPS Monolithic A/D ConverterSPECIFICATIONS (AVDD = +5 V, DRVDD = +5 V, f = 25 MSPS, VREF = 2.0 V, VINB = 2.5 V dc, T to T unles ..
AD9226 ,12-Bit, 65 MSPS Analog-to-Digital ConverterFEATURES FUNCTIONAL BLOCK DIAGRAMSignal-to-Noise Ratio: 69 dB @ f = 31 MHzINDRVDDCLK AVDDSpurious-F ..
AD9226ARS ,Complete 12-Bit, 65 MSPS ADC ConverterSPECIFICATIONS noted.)Parameter Temp Test Level Min Typ Max UnitRESOLUTION 12 BitsACCURACYIntegral ..
AD9226ARS ,Complete 12-Bit, 65 MSPS ADC ConverterSPECIFICATIONS SAMPLE MIN MAXParameters Temp Test Level Min Typ Max Unit1 1 LOGIC INPUTS (Clock, DF ..
AD9226AST ,Complete 12-Bit, 65 MSPS ADC ConverterFEATURES FUNCTIONAL BLOCK DIAGRAMSignal-to-Noise Ratio: 69 dB @ f = 31 MHzINDRVDDCLK AVDDSpurious-F ..

AD5304BRM-AD5314BRM-AD5324BRM
2.5 V to 5.5 V, 500 uA, Quad Voltage Output 8-/10-/12-Bit DACs in 10-Lead microSOIC
REV.B
2.5 V to 5.5 V, 500 �A, Quad Voltage Output
8-/10-/12-Bit DACs in 10-Lead microSOIC
FUNCTIONAL BLOCK DIAGRAMVOUTA
VDDREFIN
GND
AD5304/AD5314/AD5324VOUTBVOUTCVOUTD
SYNC
SCLK
DIN
LDAC
FEATURES
AD5304
Four Buffered 8-Bit DACs in 10-Lead microSOIC
AD5314
Four Buffered 10-Bit DACs in 10-Lead microSOIC
AD5324
Four Buffered 12-Bit DACs in 10-Lead microSOIC
Low Power Operation: 500 �A @ 3 V, 600 �A @ 5 V
2.5 V to 5.5 V Power Supply
Guaranteed Monotonic By Design Over All Codes
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V
Double-Buffered Input Logic
Output Range: 0–VREF
Power-On-Reset to Zero Volts
Simultaneous Update of Outputs (LDAC Function)
Low Power, SPI™, QSPI™, MICROWIRE™, and
DSP-Compatible 3-Wire Serial Interface
On-Chip Rail-to-Rail Output Buffer Ampliﬁers
Temperature Range –40�C to +105�C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
GENERAL DESCRIPTION
The AD5304/AD5314/AD5324 are quad 8-, 10- and 12-bit
buffered voltage output DACs in a 10-lead microSOIC package
that operate from a single 2.5 V to 5.5 V supply consuming
500 µA at 3 V. Their on-chip output ampliﬁers allow rail-to-
rail output swing to be achieved with a slew rate of 0.7 V/µs.
A 3-wire serial interface is used which operates at clock rates
up to 30 MHz and is compatible with standard SPI, QSPI,
MICROWIRE and DSP interface standards.
The references for the four DACs are derived from one reference
pin. The outputs of all DACs may be updated simultaneously
using the software LDAC function. The parts incorporate a
power-on-reset circuit that ensures that the DAC outputs power
up to zero volts and remain there until a valid write takes place
to the device. The parts contain a power-down feature that
reduces the current consumption of the device to 200 nA @ 5 V
(80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equipment.
The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, reducing
to 1 µW in power-down mode.
*. Patent No. 5,969,657; other patents pending.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
AD5304/AD5314/AD5324–SPECIFICATIONS(VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 k� to
GND; CL = 200 pF to GND; All speciﬁcations TMIN to TMAX unless otherwise noted.)
DC PERFORMANCE
OUTPUT CHARACTERISTICS
LOGIC INPUTS
POWER REQUIREMENTS
NOTESSee Terminology.Temperature range: B Version: –40°C to +105°C; typical at 25°C.DC speciﬁcations tested with the outputs unloaded.Linearity is tested using a reduced code range: AD5304 (Code 8 to 248); AD5314 (Code 28 to 995); AD5324 (Code 115 to 3981).Guaranteed by design and characterization, not production tested.In order for the ampliﬁer output to reach its minimum voltage, Offset Error must be negative. In order for the ampliﬁer output to reach its maximum voltage,
VREF = VDD and “Offset plus Gain” Error must be positive.IDD speciﬁcation is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.
Speciﬁcations subject to change without notice.
AD5304/AD5314/AD5324
AC CHARACTERISTICS1(VDD = 2.5 V to 5.5 V; RL = 2 k� to GND; CL = 200 pF to GND; all speciﬁcations TMIN to TMAX unless
otherwise noted.)
NOTESGuaranteed by design and characterization, not production tested.See Terminology.Temperature range: B Version: –40°C to +105°C; typical at 25°C.
Speciﬁcations subject to change without notice.
TIMING CHARACTERISTICS1, 2, 3
NOTESGuaranteed by design and characterization, not production tested.All input signals are speciﬁed with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.See Figure 1.
Speciﬁcations subject to change without notice.
Figure 1.Serial Interface Timing Diagram
(VDD = 2.5 V to 5.5 V. All speciﬁcations TMIN to TMAX unless otherwise noted)
AD5304/AD5314/AD5324
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = 25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . –0.3 V to VDD + 0.3 V
Reference Input Voltage to GND . . . . –0.3 V to VDD + 0.3 V
VOUTA–D to GND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . 150°C
10-Lead microSOIC Package
Power Dissipation . . . . . . . . . . . . . . . . . . (TJ max – TA)/θJA
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this speciﬁcation is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
3VOUTB
4VOUTC
6VOUTD
ORDERING GUIDE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
TERMINOLOGY
RELATIVE ACCURACY
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
Typical INL versus Code plots can be seen in Figures 4, 5, and 6.
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A speciﬁed differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed mono-
tonic by design. Typical DNL versus Code plots can be seen in
Figures 7, 8, and 9.
OFFSET ERROR
This is a measure of the offset error of the DAC and the output
ampliﬁer. It is expressed as a percentage of the full-scale range.
GAIN ERROR
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.
OFFSET ERROR DRIFT
This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
GAIN ERROR DRIFT
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
POWER-SUPPLY REJECTION RATIO (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in dBs. VREF is held at 2 V and VDD is varied ±10%.
DC CROSSTALK
This is the dc change in the output level of one DAC at midscale
in response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of another DAC. It is expressed in µV.
REFERENCE FEEDTHROUGH
This is the ratio of the amplitude of the signal at the DAC
output to the reference input when the DAC output is not being
updated. It is expressed in dBs.
MAJOR-CODE TRANSITION GLITCH ENERGY
Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC
register changes state. It is normally speciﬁed as the area of the
glitch in nV-secs and is measured when the digital code is changed
by 1 LSB at the major carry transition (011...11 to 100...00
or 100...00 to 011...11).
DIGITAL FEEDTHROUGH
Digital feedthrough is a measure of the impulse injected into the
DIGITAL CROSSTALK
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
expressed in nV-secs.
DAC-TO-DAC CROSSTALK
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk. It
is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with the LDAC bit set low
and monitoring the output of another DAC. The energy of the
glitch is expressed in nV-secs.
MULTIPLYING BANDWIDTH
The ampliﬁers within the DAC have a ﬁnite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at which
the output amplitude falls to 3 dB below the input.
TOTAL HARMONIC DISTORTION
This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC and the THD is a measure of the harmonics present
on the DAC output. It is measured in dBs.
Figure 2.Transfer Function with Negative Offset
AD5304/AD5314/AD5324
Figure 4.AD5304 Typical INL Plot
Figure 7.AD5304 Typical DNL Plot
Figure 10.AD5304 INL and DNL
Error vs. VREF
CODE
INL ERROR
LSBs2001000400600800
Figure 5.AD5314 Typical INL Plot
CODE
DNL ERROR
LSBs
2000
Figure 8.AD5314 Typical DNL Plot
TEMPERATURE – �C
ERROR
LSBs
–0.5�40040
0.4
Figure 11.AD5304 INL Error and
DNL Error vs. Temperature
CODE
INL ERROR
LSBs4000100020003000
–12
Figure 6.AD5324 Typical INL Plot
CODE
DNL ERROR
LSBs
10000
Figure 9.AD5324 Typical DNL Plot
TEMPERATURE – �C
ERROR
0.5�40040
–0.5120
Figure 12.AD5304 Offset Error and
Gain Error vs. Temperature
VDD – Volts
ERROR
0.1
Figure 13.Offset Error and Gain
Error vs. VDD
VDD – Volts
2.53.04.04.55.53.55.0
Figure 16.Supply Current vs. Supply
Voltage
Figure 19.Half-Scale Settling (1/4 to
3/4 Scale Code Change)
Figure 14.VOUT Source and Sink
Current Capability
VDD – Volts
2.53.04.04.55.53.55.0
Figure 17.Power-Down Current vs.
Supply Voltage
CH1
CH2
CH1 2V, CH2 200mV, TIME BASE = 200�s/DIV
Figure 20.Power-On Reset to 0 V
Figure 15.Supply Current vs. DAC
Code
Figure 18.Supply Current vs. Logic
Input Voltage
Figure 21.Exiting Power-Down to
Midscale
AD5304/AD5314/AD5324
Figure 22.IDD Histogram with
VDD = 3 V and VDD = 5 V
VREF – Volts
FULL-SCALE ERROR
Volts
–0.01
Figure 25.Full-Scale Error vs. VREF
Figure 23.AD5324 Major-Code
Transition Glitch Energy
Figure 26.DAC-to-DAC Crosstalk
FREQUENCY – kHz
0.11101001k10k
–60
Figure 24.Multiplying Bandwidth
(Small-Signal Frequency Response)

Partno	Mfg	Dc	Qty	Available	Descript
AD5304BRM	AD	N/a	2	avai	2.5 V to 5.5 V, 500 uA, Quad Voltage Output 8-/10-/12-Bit DACs in 10-Lead microSOIC
AD5314BRM	AD	N/a	3	avai	2.5 V to 5.5 V, 500 uA, Quad Voltage Output 8-/10-/12-Bit DACs in 10-Lead microSOIC
AD5324BRM	AD	N/a	2	avai	2.5 V to 5.5 V, 500 uA, Quad Voltage Output 8-/10-/12-Bit DACs in 10-Lead microSOIC