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AD53041KRPADN/a246avaiHigh Speed Active Load with Inhibit Mode
AD53041KRPADIN/a2avaiHigh Speed Active Load with Inhibit Mode


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AD53041KRP
High Speed Active Load with Inhibit Mode
REV.A
High Speed Active Load
with Inhibit Mode
FUNCTIONAL BLOCK DIAGRAMFEATURES

650 mA Voltage Programmable Current Range
Three Selectable Gain Ranges
1.7 ns Propagation Delay
Inhibit Mode Function
High Speed Differential Inputs for Maximum Flexibility
Ultrasmall 20-Lead PSOP Package with Built-In Heatsink
APPLICATIONS
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
PRODUCT DESCRIPTION

The AD53041 is a complete, high speed, current switching load
designed for use in linear, digital or mixed signal test systems.
Combining a high speed monolithic process with a unique sur-
face mount package, this product attains superb electrical per-
formance while preserving optimum packaging densities in an
ultrasmall 20-lead, PSOP package with a built-in heatsink.
Featuring current programmability of up to –50 mA, the
AD53041 is designed to force the device under test to source
or sink the programmed IOH and IOL currents. IOH and IOL
currents are determined by applying a corresponding voltage
(5 V = 50 mA, 16 mA, 5 mA) to the IOHPGM and IOLPGM pins.
The voltage-to-current conversion is performed within the
AD53041, thus allowing the current levels to be set by a stan-
dard voltage out digital-to-analog converter.
The AD53041 transition from IOH to IOL occurs when the out-
put voltage of the device under test slews above or below the
programmed threshold or commutation voltage. The commuta-
tion voltage is programmable from –2 V to +7 V, covering the
large spectrum of logic devices while able to support the large
current specifications (48 mA) typically associated with line
drivers. To test I/O devices, the active load can be switched into
a high impedance state (Inhibit Mode), electrically removing the
active load from the path through the Inhibit Mode feature. The
active load leakage current in Inhibit is typically 100 nA.
The Inhibit input circuitry is implemented using high speed
differential inputs with a common-mode voltage range ofV to +3 V and a maximum differential voltage of 3 V. This
allows for direct interface to precision differential ECL timing or
the simplicity of switching active load from a single ended TTL
or CMOS logic source. With switching speeds from IOH or IOL
into Inhibit of less than 2.0 ns, the AD53041 can be electrically
removed from the signal path “on the fly.”
The AD53041 is available in a 20-lead, PSOP package with a
built-in-heatsink and is specified to operate over the ambient
commercial temperature range from –25°C to +85°C.
VCC
VEE
INH
INH
IOHPGM
VCOMIN
IOLPGM
GAINA
GAINB
TO DUT
NOT SHOWN: THE AGND PINS ARE THE HIGH QUALITY GROUND
REFERENCE FOR THE VOLTAGE-TO-CURRENT CONVERTERS.
THE GND PINS PROVIDE RETURN PATHS FOR INTERNAL CURRENTS.
VCC IS THE POSITIVE SUPPLY, VEE IS THE NEGATIVE SUPPLY.
ALL GROUND PINS SHOULD BE CONNECTED TO THE SYSTEM
ANALOG GROUND PLANE.

Figure 1.Typical Application Circuit
IOLOUT
IOLRTN
IOHRTN
IOHOUT
VCOMOUT
INH
INH
IOHPGM
VCOMIN
OUT_SENSE
IOLPGM
GAINB
GAINA
AD53041–SPECIFICATIONS(All specifications apply at TJ = +858C 6 58C. +VS = +10.5 V 6 3%, –VS =
–5.2 V 6 3% unless otherwise specified. VCOMOUT is bypassed to ground with a series RC consisting of a 1 V resistor and a 0.1 mF capacitor,
and is also connected directly to OUT_SENSE. All temperature coefficients are characterized over TJ = 758C–958C.)
AD53041
POWER SUPPLIES
NOTES
Typical values are not tested or guaranteed.
Specifications subject to change without notice.
Table I.Active Load Truth Table
(Including External Diode Bridge per Figure 1; Scale Factors per Functional Block Diagram)
Vact–
Vact+
VDUT
VDUT
ECL+
ECL–
PROPAGATION DELAY LOAD AND TEST CONDITIONS
AD53041
C3004a–0–11/98
PRINTED IN U.S.A.
CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD53041 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1

Power Supply Voltage
+VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+12 V
–VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–7 V
+VS to –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+17 V
GND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.4 V
Inputs
INH, INH . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6 V, –3 V
INH to INH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–3 V
GAINA, GAINB . . . . . . . . . . . . . . . . . . . . . . . .+6 V, –3 V
GAINA to GAINB . . . . . . . . . . . . . . . . . . . . . . . . . . . .–5 V
VCOMIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8 V, –3 V
IOHPGM, IOLPGM . . . . . . . . . . . . . . . . . . . . . . . . .+6 V, –1 V
Outputs
IOHOUT, IOHRTN . . . . . . . . . . . . . . . . . . . . . . . .+9 V, –2.5 V
IOLOUT, IOLRTN . . . . . . . . . . . . . . . . . . . . . . . . .+8 V, –3.5 V
VCOMOUT Short Circuit Duration . . . . . . . . .Not Protected2
Environmental
Operating Temperature (Junction) . . . . . . . . . . . . . .+175°C
Storage Temperature . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec)3 . . . . . . . . . .+260°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Absolute maximum limits apply
individually, not in combination. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.Short circuit to ground or to either supply will result in the destruction of the
device.To ensure lead coplanarity (–0.002 inches) and solderability, handling with bare
hands should be avoided and the device should be stored in environments at 24°C 5°C (75°F – 10°F) with relative humidity not to exceed 65%.
PIN CONFIGURATION
PACKAGE THERMAL CHARACTERISTICS
OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).
20-Lead Thermally Enhanced
Power Small Outline Package (PSOP)
(RP-20)
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0201 (0.51)
0.0130 (0.33)
0.1043 (2.65)
0.0926 (2.35)
(1.27)
BSCSTANDOFF
0.0500 (1.27)
0.0057 (0.40)
0.0295 (0.75)
0.0098 (0.25)x 45°
0.5118 (13.00)
0.4961 (12.60)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
0.3340 (8.61)
0.3287 (8.35)
HEAT
SINK
ORDERING GUIDE
AGND
VCC
DGND
GAINA
GAINB
IOLPGM
IOLOUT
IOLRTN
VEE
INH
INHVCOMIN
VCOMOUT
IOHRTN
IOHOUT
DGND
DGNDIOHPGM
AGND
DGND
DIMPLE ON BOTTOM
OF PACKAGE
NOTES:
AGND IS THE HIGH-QUALITY GROUND REFERENCE
FOR IOLPGM AND IOHPGM.
DGND IS THE SUPPLY GROUND.
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