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AD53040KRP
Ultrahigh Speed Pin Driver with Inhibit Mode
REV.B
Ultrahigh Speed Pin Driver
with Inhibit Mode
FUNCTIONAL BLOCK DIAGRAM
FEATURES
500 MHz Driver Operation
Driver Inhibit Function
100 ps Edge Matching
Guaranteed Industry Specifications
50 V Output Impedance
>1.5 V/ns Slew Rate
Variable Output Voltages for ECL, TTL and CMOS
High Speed Differential Inputs for Maximum Flexibility
Ultrasmall 20-Lead SOP Package with Built-In Heat Sink
APPLICATIONS
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
Instrumentation and Characterization Equipment
PRODUCT DESCRIPTIONThe AD53040 is a complete high speed pin driver designed for
use in digital or mixed-signal test systems. Combining a high
speed monolithic process with a unique surface mount package,
this product attains superb electrical performance while preserv-
ing optimum packaging densities and long-term reliability in an
ultrasmall 20-lead, SOP package with built-in heat sink.
Featuring unity gain programmable output levels of –3 V to
+8 V, with output swing capability of less than 100 mV to 9 V,
the AD53040 is designed to stimulate ECL, TTL and CMOS
logic families. The 500 MHz data rate capacity and matched
output impedance allows for real-time stimulation of these
digital logic families. To test I/O devices, the pin driver can
be switched into a high impedance state (Inhibit Mode), electri-
cally removing the driver from the path. The pin driver leakage
current inhibit is typically 100 nA and output charge transfer
entering inhibit is typically less than 20 pC.
The AD53040 transition from HI/LO or to inhibit is controlled
through the data and inhibit inputs. The input circuitry uses
high speed differential inputs with a common-mode range of3 V. This allows for direct interface to precision differential
ECL timing or the simplicity of stimulating the pin driver from a
single ended TTL or CMOS logic source. The analog logic HI/LO
inputs are equally easy to interface. Typically requiring 10 mA of
bias current, the AD53040 can be directly coupled to the
output of a digital-to-analog converter.
The AD53040 is available in a 20-lead, SOP package with a
built-in heat sink and is specified to operate over the ambient
commercial temperature range of –25°C to +85°C.
AD53040–SPECIFICATIONS(All specifications are at TJ = +858C 6 58C, +VS = +12 V 6 3%, –VS = –7 V 6
3% unless otherwise noted. All temperature coefficients are measured at TJ = +758C–958C). (A 39 nF capacitor must be connected between
VCC and VHDCPL and between VEE and VLDCPL.)
AD53040
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD53040 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
NOTES
Connecting or shorting the decoupling capacitors to ground will result in the destruction of the device.
Specifications subject to change without notice.
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS1Power Supply Voltage
+VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+13 V
–VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–8 V
+VS to –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+20 V
Inputs
DATA, DATA, INH, INH . . . . . . . . . . . . . . . .+5 V, –3 V
DATA to DATA, INH to INH . . . . . . . . . . . . . . . . . .–3 V
VH, VL to GND . . . . . . . . . . . . . . . . . . . . . . . . .+9 V, –4 V
VH to VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+11 V, 0 V
Outputs
VOUT Short Circuit Duration . . . . . . . . . . . . . . . .Indefinite2
VOUT Range in Inhibit Mode
VHDCPL . . . . . Do Not Connect Except for Capacitor to VCC
VLDCPL . . . . . Do Not Connect Except for Capacitor to VEE
THERM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+13 V, 0 V
Environmental
Operating Temperature (Junction) . . . . . . . . . . . . . .+175°C
Storage Temperature . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec)3 . . . . . . . . . .+260°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Absolute maximum limits apply
individually, not in combination. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
2Output short circuit protection is guaranteed as long as proper heat sinking is
employed to ensure compliance with the operating temperature limits.
3To ensure lead coplanarity (–0.002 inches) and solderability, handling with bare
hands should be avoided and the device should be stored in environments at 24°C 5°C (75°F – 10°F) with relative humidity not to exceed 65%.
AD53040
PIN FUNCTION DESCRIPTIONSVEE
GND
VHDCPL
INH, INH
DATA,
DATA
TVCC
PIN CONFIGURATION
VCC
GND
TVCC
THERM
VCC
VHDCPL
GND
GND
GNDVOUT
GND
VLDCPL
VEE
VEE
INHINH
DATA
DATA
Table I.Pin Driver Truth Table
Table II.Package Thermal Characteristics
APPLICATION INFORMATION
Power Supply Distribution, Bypassing and SequencingThe AD53040 draws substantial transient currents from its
power supplies when switching between states and careful design
of the power distribution and bypassing is key to obtaining speci-
fied performance. Supplies should be distributed using broad,
low inductance traces or (preferably) planes in a multilayered
board with a dedicated ground-plane layer. All of the device’s
power supply pins should be used to minimize the internal in-
ductance presented by the part’s bond wires. Each supply must
be bypassed to ground with at least one 0.1 mF capacitor; chip-
style capacitors are preferable as they minimize inductance. One
or more 10 mF (or greater) Tantalum capacitors per board are
also advisable to provide additional local energy storage.
The AD53040’s current-limit circuitry also requires external
bypass capacitors. Figure 1 shows a simplified schematic of the
positive current-limit circuit. Excessive collector current in out-
put transistor Q49 creates a voltage drop across the 10 W resis-
tor, which turns on PNP transistor Q48. Q48 diverts the rising-
edge slew current, shutting down the current mirror and remov-
ing the output stage’s base drive. The VHDCPL pin should be
bypassed to the positive supply with a 0.039 mF capacitor, while
the VLDCPL pin (not shown) requires a similar capacitor to the
negative supply- these capacitors ensure that the AD53040
doesn’t current limit during normal output transitions up the its
full 9 V rated step size. Both capacitors must have minimum-
length connections to the AD53040. Here again, chip capacitors
are ideal.
Figure 1.Simplified Schematic of the AD53040 Output
Stage and Positive Current Limit Circuitry
Several points about the current-limit circuitry should be noted.
First, the limiting currents are not tightly controlled, as they are
functions of both absolute transistor VBES and junction tem-
perature; higher dc output current is available at lower junction
temperatures. Second, it is essential to connect the VHDCPL
capacitor to the positive supply (and the VLDCPL capacitor to
the negative supply)—failure to do so causes considerable ther-
mal stress in the current-limiting resistor(s) during normal sup-
ply sequencing and may ultimately cause them to fail, rendering
the part nonfunctional. Finally, the AD53040 may appear to
function normally for small output steps (less than 3 V or so) if
one or both of these capacitors is absent, but it will exhibit
excessive rise or fall times for steps of larger amplitude.
The AD53040 does not require special power-supply sequencing.
However, good design practice dictates that digital and analog
control signals not be applied to the part before the supplies are
stable. Violating this guideline will not normally destroy the
part, but the active inputs can draw considerable current until
the main supplies are applied.
Digital Input Range RestrictionsTotal range amongst all digital signals (DATA, DATA, INH,
and INH) has to be less than or equal to 2 V to meet specified
timing. The device will function above 2 V with reduced perfor-
mance up to the absolute maximum limit. This performance
degradation might not be noticed in all modes of operation. Of
all the six possible transitions (VH v VL, VL v VH, VH v INH,
INH v VH, VL v INH and INH v VL), there may be only one
that would show a degradation, usually in delay time. Taken to
the extreme, the driver may fail to achieve a proper output volt-
age, output impedance or may fail to fully inhibit.
An example of a scenario that would not work for the AD53040
is if the part is driven using 5 V single-ended CMOS. One pin of
each differential input would be tied to a +2.5 V reference level
and the logic voltages would be applied to the other. This would
meet the Absolute Maximum Rating of –3 V because the max
differential is –2.5 V. It is however possible, for example for
0.0 V to be applied to the INH input and +5 V to be applied to
the DATA input. This 5 V difference far exceeds the 2.0 V
limitation given above. Even using 3 V CMOS or TTL the
difference between logic high and logic low is greater than or
equal to 3 V which will not properly work. The only solution is
to use resistive dividers or equivalent to reduce the voltage levels.
AD53040
–2V
C12
0.01mF
50V
VLOW
–2V
C15
0.1mF
C13
0.01mF
C17
0.039mFVOUT
C11
0.1mF
VEE
–VS
+VS
VCC
GND
JP1
DATA
INH
SMB
SMB
DB15
VLOW
VHIGH
–2V
–VS
THERM
–5.2V
+VS
–5.2V
NOTE:50V TERMINATION TO BE AS CLOSE TO RECEIVER
AS POSSIBLE. (END OF TRACE MARKED BY *). THROUGH
SMA CONNECTS BETWEEN MC10EL16 OUTPUTS AND DUT.NO VIAS ALLOWED ON VOUT LINE.SMA ON VOUT TO BE MOUNTED ON ITS SIDE FOR BEST
IMPEDANCE MATCH.
4. ONE DIMENSION OF BOARD TO BE 4-1/2 INCHES.
5. DUT PACKAGE IS TO BE CENTERED ON BOARD.
6. ALL RESISTORS AND NONELECTROLYTIC CAPS ARE
0805-SIZE SURFACE MOUNT.SEE DATA SHEET FOR HIDDEN POWER AND GROUND PINS
ON LOGIC GATES.
8. ALL 100nF BYPASS CAPACITORS TO BE LOCATED CLOSE
TO PACKAGE.
9. PCB IS TO BE 4-LAYER WITH POWER GND ( ) AND –2V AS
0.1mF
SIDESMBFigure 3.Evaluation Board Schematic
