AD5302BRM-AD5312BRM-AD5322BRM Fast Delivery |IC PHOENIX CO.,LIMITED

AD5302BRM ,+2.5 V to +5.5 V, 230 uA Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACsspecifications T to T unless otherwise noted.)L MIN MAX2 B Version1Parameter Min Typ Max ..
AD5302BRMZ , 2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs
AD53032JSTP ,High Performance Driver/Comparator Active Load on a Single Chipfeatures built-in latches and ECL-compatible IOHRTNoutputs. The outputs are capable of driving 50 ..
AD53033JSTP ,DRIVER/COMPARATOR: High Performance Driver/Comparator on a Single Chipfeatures built-in latches and ECL-compatibleoutputs. The outputs are capable of driving 50 W signa ..
AD53040KRP ,Ultrahigh Speed Pin Driver with Inhibit ModeCHARACTERISTICSLogic High Range –2 +8 Volts DATA = H, V = –2 V to +8 VHV = –3 V (V = –2 V to +6 V)L ..
AD53041KRP ,High Speed Active Load with Inhibit ModeAPPLICATIONSIOLRTNAutomatic Test EquipmentIOHRTNSemiconductor Test Systems INHIOHOUTBoard Test Syst ..
AD9200KST ,Complete 10-Bit, 20 MSPS, 80 mW CMOS A/D ConverterFEATURESA single clock input is used to control all internal conversionCMOS 10-Bit, 20 MSPS Samplin ..
AD9200KSTRL ,Complete 10-Bit, 20 MSPS, 80 mW CMOS A/D ConverterFEATURESA single clock input is used to control all internal conversionCMOS 10-Bit, 20 MSPS Samplin ..
AD9201ARS ,Dual Channel, 20 MHz 10-Bit Resolution CMOS ADCSPECIFICATIONS internal ref, differential input signal, unless otherwise noted)Parameter Symbol Min ..
AD9201ARSZ , Dual Channel, 20 MHz 10-Bit Resolution CMOS ADC
AD9203ARU ,10-Bit, 40 MSPS, 3 V, 74 mW A/D ConverterSPECIFICATIONSMIN MAXParameter Symbol Min Typ Max Units ConditionsRESOLUTION 10 BitsMAX CONVERSION ..
AD9212ABCPZ-65 , Octal, 10-Bit, 40 MSPS/65 MSPS, Serial LVDS, 1.8 V ADC

AD5302BRM-AD5312BRM-AD5322BRM
+2.5 V to +5.5 V, 230 uA Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs
REV.0
+2.5 V to +5.5 V, 230 mA Dual Rail-to-Rail,
Voltage Output 8-/10-/12-Bit DACs
FUNCTIONAL BLOCK DIAGRAM
VOUTA
VOUTB
VDDVREFA
VREFB
SYNC
SCLK
DIN
LDACGND
FEATURES
AD5302: Two 8-Bit Buffered DACs in One Package
AD5312: Two 10-Bit Buffered DACs in One Package
AD5322: Two 12-Bit Buffered DACs in One Package
10-Lead mSOIC Package
Micropower Operation: 300 mA @ 5 V (Including
Reference Current)
Power-Down to 200 nA @ 5 V, 50 nA @ 3 V
+2.5 V to +5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic By Design Over All Codes
Buffered/Unbuffered Reference Input Options
0–VREF Output Voltage
Power-On-Reset to Zero Volts
Simultaneous Update of DAC Outputs via LDAC
Low Power Serial Interface with Schmitt-Triggered
Inputs
On-Chip Rail-to-Rail Output Buffer Amplifiers
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
GENERAL DESCRIPTION
The AD5302/AD5312/AD5322 are dual 8-, 10- and 12-bit buff-
ered voltage output DACs in a 10-lead mSOIC package that
operate from a single +2.5 V to +5.5 V supply consuming
230 mA at 3 V. Their on-chip output amplifiers allow the outputs
to swing rail-to-rail with a slew rate of 0.7 V/ms. The AD5302/
AD5312/AD5322 utilize a versatile 3-wire serial interface which
operates at clock rates up to 30 MHz and is compatible with
standard SPI™, QSPI™, MICROWIRE™ and DSP interface
standards.
The references for the two DACs are derived from two reference
pins (one per DAC). The reference inputs may be configured as
buffered or unbuffered inputs. The outputs of both DACs may
be updated simultaneously using the asynchronous LDAC in-
put. The parts incorporate a power-on-reset circuit that ensures
that the DAC outputs power-up to 0 V and remain there until a
valid write takes place to the device. The parts contain a power-
down feature that reduces the current consumption of the
devices to 200 nA at 5 V (50 nA at 3 V) and provides software-
selectable output loads while in power-down mode.
The low power consumption of these parts in normal operation
make them ideally suited to portable battery operated equip-
ment. The power consumption is 1.5 mW at 5 V, 0.7 mW at
3 V, reducing to 1 mW in power-down mode.
*Patent Pending; protected by U.S. Patent No. 5684481.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
AD5302/AD5312/AD5322–SPECIFICATIONS(VDD = +2.5 V to +5.5 V; VREF = +2 V; RL = 2 kV
to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless otherwise noted.)
OUTPUT CHARACTERISTICS
POWER REQUIREMENTS
NOTESSee Terminology.Temperature range: B Version: –40°C to +105°C.DC specifications tested with the outputs unloaded.Linearity is tested using a reduced code range: AD5302 (Code 8 to 248); AD5312 (Code 28 to 995); AD5322 (Code 115 to 3981).Guaranteed by design and characterization, not production tested.In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage,
VREF = VDD and “Offset plus Gain” Error must be positive.
AD5302/AD5312/AD5322
AC CHARACTERISTICS1(VDD = +2.5 V to +5.5 V; RL = 2 kV to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless
otherwise noted.)
NOTESGuaranteed by design and characterization, not production tested.See Terminology.Temperature range: B Version: –40°C to +105°C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2, 3
NOTESGuaranteed by design and characterization, not production tested.All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.See Figure 1.
Specifications subject to change without notice.
(VDD = +2.5 V to +5.5 V; all specifications TMIN to TMAX unless otherwise noted)
SCLK
SYNC
DIN*
LDAC
LDAC
*SEE PAGE 11 FOR DESCRIPTION OF INPUT REGISTER
AD5302/AD5312/AD5322
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5302/AD5312/AD5322 features proprietary ESD protection circuitry, perma-
nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . . .–0.3 V to VDD + 0.3 V
Reference Input Voltage to GND . . . . .–0.3 V to VDD + 0.3 V
VOUTA, VOUTB to GND . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . .–40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature (TJ Max) . . . . . . . . . . . . . . . . . .+150°C
10-Lead mSOIC Package
Power Dissipation . . . . . . . . . . . . . . . . . . .(TJ Max–TA)/qJAJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .206°C/WJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .44°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
AD5312BRM
PIN CONFIGURATION
LDAC
VDD
VREFB
VREFA
VOUTA
GND
DIN
SCLK
SYNC
VOUTB
PIN FUNCTION DESCRIPTIONS
3VREFB
4VREFA
5VOUTA
TERMINOLOGY
RELATIVE ACCURACY
For the DAC, relative accuracy or Integral Nonlinearity (INL)
is a measure of the maximum deviation, in LSBs, from a straight
line passing through the actual endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure 4.
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of –1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot can be seen
in Figure 7.
OFFSET ERROR
This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.
GAIN ERROR
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.
OFFSET ERROR DRIFT
This is a measure of the change in offset error with changes in
GAIN ERROR DRIFT
This is a measure of the change in gain error with changes in tem-
perature. It is expressed in (ppm of full-scale range)/°C.
MAJOR-CODE TRANSITION GLITCH ENERGY
Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC regis-
ter changes state. It is normally specified as the area of the glitch
in nV-secs and is measured when the digital code is changed by
1 LSB at the major carry transition (011...11 to 100...00 or
100...00 to 011...11).
DIGITAL FEEDTHROUGH
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital input pins of the
device, but is measured when the DAC is not being written to
(SYNC held high). It is specified in nV-secs and is measured
with a full-scale change on the digital input pins, i.e., from all 0s
to all 1s and vice versa.
ANALOG CROSSTALK
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of the other DAC. It is measured
by loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa) while keeping LDAC high. Then
pulse LDAC low and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
AD5302/AD5312/AD5322
DAC-TO-DAC CROSSTALK
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
the other DAC. This includes both digital and analog crosstalk.
It is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) while keeping LDAC low
and monitoring the output of the other DAC. The area of the
glitch is expressed in nV-secs.
DC CROSSTALK
This is the dc change in the output level of one DAC in re-
sponse to a change in the output of the other DAC. It is mea-
sured with a full-scale output change on one DAC while
monitoring the other DAC. It is expressed in mV.
POWER-SUPPLY REJECTION RATIO (PSRR)
This indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change in
VOUT to a change in VDD for full-scale output of the DAC. It is
measured in dBs. VREF is held at +2 V and VDD is varied –10%.
REFERENCE FEEDTHROUGH
This is the ratio of the amplitude of the signal at the DAC out-
put to the reference input when the DAC output is not being
updated (i.e., LDAC is high). It is expressed in dBs.
TOTAL HARMONIC DISTORTION
This is the difference between an ideal sine wave and its attenu-
ated version using the DAC. The sine wave is used as the refer-
ence for the DAC and the THD is a measure of the harmonics
present on the DAC output. It is measured in dBs.
MULTIPLYING BANDWIDTH
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
CHANNEL-TO-CHANNEL ISOLATION
This is a ratio of the amplitude of the signal at the output of one
DAC to a sine wave on the reference input of the other DAC. It
is measured in dBs.
PLUS
OUTPUT
VOLTAGE
POSITIVE
OFFSET
ERROR
NEGATIVE
OFFSET
ERROR
AMPLIFIER
FOOTROOM
(1mV)
Figure 2.Transfer Function with Negative Offset

OUTPUT
VOLTAGE
POSITIVE
OFFSET
ERROR
PLUS
Figure 3.Transfer Function with Positive Offset
CODE
INL ERROR – LSBs
–0.5
Figure 4.AD5302 Typical INL Plot

CODE
DNL ERROR – LSBs50250100150200
0.2
Figure 7.AD5302 Typical DNL Plot
VREF – Volts
ERROR – LSBs45
–.75
Figure 10.AD5302 INL and DNL
Error vs. VREF
CODE
INL ERROR – LSBs2001000400600800
Figure 5.AD5312 Typical INL Plot
CODE
DNL ERROR – LSBs
2000
Figure 8.AD5312 Typical DNL Plot

TEMPERATURE – 8C
ERROR – LSBs
MAX INLMAX DNL
MIN DNLMIN INL
Figure 11.AD5302 INL Error and
DNL Error vs. Temperature
CODE
INL ERROR – LSBs4000100020003000
–12
Figure 6.AD5322 Typical INL Plot
CODE
DNL ERROR – LSBs
–0.5
Figure 9.AD5322 Typical DNL Plot

TEMPERATURE – 8C
ERROR – %
0.5
Figure 12.Offset Error and Gain
Error vs. Temperature
AD5302/AD5312/AD5322

SINK/SOURCE CURRENT – mA
OUT
– Volts01236
Figure 14.Source and Sink Current
Capability
VDD – Volts
IDD
–
Figure 17.Power-Down Current vs.
Supply Voltage
CH1 1V, CH2 1V, TIME BASE = 20ms/DIV
CH2
CH1
Figure 20.Power-On Reset to 0 V
IDD
–
600ZERO-SCALEFULL-SCALE
300
Figure 15.Supply Current vs. Code

Figure 18.Supply Current vs. Logic
Input Voltage
CH1 1V, CH3 5V, TIME BASE = 1ms/DIV
CH3
CH1
Figure 21.Exiting Power-Down to
Midscale

IDD – mA
FREQUENCY100150400200250350300
Figure 13.IDD Histogram with VDD =
+3 V and VDD = +5 V
VDD – Volts
IDD
–
400
Figure 16.Supply Current vs. Supply
Voltage

CH1 1V, CH2 5V, TIME BASE = 5ms/DIV
CH2
CH1
Figure 19.Half-Scale Settling (1/4 to
3/4 Scale Code Change)

Partno	Mfg	Dc	Qty	Available	Descript
AD5302BRM	AD	N/a	3639	avai	+2.5 V to +5.5 V, 230 uA Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs
AD5312BRM	AD	N/a	1300	avai	+2.5 V to +5.5 V, 230 uA Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs
AD5322BRM	AD	N/a	50	avai	+2.5 V to +5.5 V, 230 uA Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs