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AD5302ARM-AD5312ARM-AD5322ARM
2.5 V to 5.5 V, 230 µA, Dual Rail-to-Rail Voltage Output 8-Bit DAC in a 10-Lead MicroSOIC Package
REV.A
2.5 V to 5.5 V, 230 �A Dual Rail-to-Rail,
Voltage Output 8-/10-/12-Bit DACs*Patent Pending; protected by U.S. Patent No. 5684481.
FEATURES
AD5302: Two 8-Bit Buffered DACs in 1 Package
A Version: �1 LSB INL, B Version: �0.5 LSB INL
AD5312: Two 10-Bit Buffered DACs in 1 Package
A Version: �4 LSB INL, B Version: �2 LSB INL
AD5322: Two 12-Bit Buffered DACs in 1 Package
A Version: �16 LSB INL, B Version: �8 LSB INL
10-Lead MSOP Package
Micropower Operation: 300 �A @ 5 V (Including
Reference Current)
Power-Down to 200 nA @ 5 V, 50 nA @ 3 V
2.5 V to 5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design over All Codes
Buffered/Unbuffered Reference Input Options
0 V to VREF Output Voltage
Power-On-Reset to 0 V
Simultaneous Update of DAC Outputs via LDAC
Low Power Serial Interface with Schmitt-Triggered Inputs
On-Chip Rail-to-Rail Output Buffer Amplifiers
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
FUNCTIONAL BLOCK DIAGRAM
VOUTA
VOUTB
VDDVREFA
VREFB
SYNC
SCLK
DIN
LDACGND
GENERAL DESCRIPTIONThe AD5302/AD5312/AD5322 are dual 8-, 10-, and 12-bit buffered
voltage output DACs in a 10-lead MSOP package that operate from
a single 2.5 V to 5.5 V supply, consuming 230 µA at 3 V. Their
on-chip output amplifiers allow the outputs to swing rail-to-rail
with a slew rate of 0.7 V/µs. The AD5302/AD5312/AD5322
utilize a versatile 3-wire serial interface that operates at clock rates
up to 30 MHz and is compatible with standard SPI®, QSPI™,
MICROWIRE™, and DSP interface standards.
The references for the two DACs are derived from two reference
pins (one per DAC). The reference inputs may be configured as
buffered or unbuffered inputs. The outputs of both DACs may be
updated simultaneously using the asynchronous LDAC input. The
parts incorporate a power-on reset circuit, which ensures that the
DAC outputs power-up to 0 V and remain there until a valid write
takes place to the device. The parts contain a power-down feature
that reduces the current consumption of the devices to 200 nA at
5V (50 nA at 3 V) and provides software-selectable output loads
while in power-down mode.
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery operated equipment.
The power consumption is 1.5 mW at 5 V, 0.7 mW at 3 V, reducing
to 1 µW in power-down mode.
AD5302/AD5312/AD5322–SPECIFICATIONS(VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 k� to
GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.)DAC REFERENCE INPUTS
OUTPUT CHARACTERISTICS
LOGIC INPUTS
POWER REQUIREMENTS
NOTESSee Terminology section.Temperature range: A, B Version: –40°C to +105°C.DC specifications tested with the outputs unloaded.Linearity is tested using a reduced code range: AD5302 (Code 8 to 248); AD5312 (Code 28 to 995); AD5322 (Code 115 to 3981).
AD5302/AD5312/AD5322
AC SPECIFICATIONS1Slew Rate
Major-Code Transition Glitch Energy
Digital Feedthrough
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
NOTESGuaranteed by design and characterization, not production tested.See Terminology section.Temperature range: A, B Version: –40°C to +105°C.
Specifications subject to change without notice.
(VDD = 2.5 V to 5.5 V; RL = 2 k� to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless
otherwise noted.)NOTESGuaranteed by design and characterization, not production tested.All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.See Figure 1.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2, 3(VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.)
AD5302/AD5312/AD5322
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5302/AD5312/AD5322 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1, 2(TA = 25°C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . .–0.3 V to VDD + 0.3 V
Reference Input Voltage to GND . . . . .–0.3 V to VDD + 0.3 V
VOUTA, VOUTB to GND . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (A, B Version) . . . . . . . . . . . . . .–40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature (TJ Max) . . . . . . . . . . . . . . . . .+150°C
10-Lead MSOP Package
Power Dissipation . . . . . . . . . . . . . . . . . . . .(TJ Max–TA)/�JA
PIN CONFIGURATION �JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .206°C/W
�JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .44°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .220°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
PIN FUNCTION DESCRIPTIONS3VREFBReference Input Pin for DAC B. This is the reference for DAC B. It may be configured as a buffered or
5VOUTABuffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
TERMINOLOGY
Relative AccuracyFor the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSB, from a straight
line passing through the actual endpoints of the DAC transfer
function. A typical INL versus code plot can be seen in TPC 1.
Differential NonlinearityDifferential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL versus code plot can be
seen in TPC 4.
Offset ErrorThis is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.
Gain ErrorThis is a measure of the span error of the DAC. It is the devia-
tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.
Offset Error DriftThis is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Gain Error DriftThis is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Major-Code Transition Glitch EnergyMajor-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC regis-
ter changes state. It is normally specified as the area of the glitch
in nV-secs and is measured when the digital code is changed by
1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or
100 . . . 00 to 011 . . . 11).
Digital FeedthroughDigital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital input pins of the
device, but is measured when the DAC is not being written to
(SYNC held high). It is specified in nV-secs and is measured
with a full-scale change on the digital input pins, i.e., from all 0s
to all 1s and vice versa.
Analog CrosstalkThis is the glitch impulse transferred to the output of one DAC
due to a change in the output of the other DAC. It is measured
by loading one of the input registers with a full-scale code
change (all 0s to all 1s and vice versa) while keeping LDAC
high. Then pulse LDAC low and monitor the output of the
DAC whose digital code was not changed. The area of the glitch
is expressed in nV-secs.
