AD5301BRM-AD5311BRM-AD5321BRM Fast Delivery |IC PHOENIX CO.,LIMITED

AD5311BRM ,+2.5 V to +5.5 V, 120 uA, 2-Wire Interface, Voltage Output 8-/10-/12-Bit DACsFEATURESThe AD5301/AD5311/AD5321 are single 8-, 10- and 12-bitAD5301: Buffered Voltage Output 8-Bit ..
AD5311BRM-REEL , 2.5 V to 5.5 V, 120 μA, 2-Wire Interface, Voltage-Output 8-/10-/12-Bit DACs
AD5311BRT-REEL7 , 2.5 V to 5.5 V, 120 μA, 2-Wire Interface, Voltage-Output 8-/10-/12-Bit DACs
AD5312ARM ,2.5 V to 5.5 V, 230 µA, Dual Rail-to-Rail Voltage Output 10-Bit DACspecifications T to T , unless otherwise noted.)L MIN MAX2 2 A Version B Version1Parameter ..
AD5312BRM ,+2.5 V to +5.5 V, 230 uA Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACsGENERAL DESCRIPTIONAD5302: Two 8-Bit Buffered DACs in One Package The AD5302/AD5312/AD5322 are dual ..
AD5312BRM-REEL , 2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs
AD9221AR ,Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D ConvertersSPECIFICATIONS otherwise noted)Parameter AD9221 AD9223 AD9220 UnitsRESOLUTION 12 12 12 Bits minMAX ..
AD9222BCPZ-50 , Octal, 12-Bit, 40/50 MSPS Serial LVDS 1.8 V A/D Converter
AD9223 ,12-Bit, 1.5/3.0/10 MSPS A/D ConvertersGENERAL DESCRIPTION and beyond the Nyquist rate. Also, the AD9221/AD9223/AD9220The AD9221, AD9223, ..
AD9223AR ,Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D ConvertersSPECIFICATIONS(AVDD = +5 V, DVDD = +5 V, f = Max Conversion Rate, V = 2.5 V, VINB = 2.5 V, T to T u ..
AD9223AR-REEL ,12-Bit, 3.0 MSPS A/D ConverterGENERAL DESCRIPTION and beyond the Nyquist rate. Also, the AD9221/AD9223/AD9220The AD9221, AD9223, ..
AD9223ARS ,Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D ConvertersSPECIFICATIONS Ended Input T to T unless otherwise noted)MIN MAXParameters AD9221 AD9223 AD9220 Uni ..

AD5301BRM-AD5311BRM-AD5321BRM
+2.5 V to +5.5 V, 120 uA, 2-Wire Interface, Voltage Output 8-/10-/12-Bit DACs
REV. 0
+2.5 V to +5.5 V, 120 mA, 2-Wire Interface,
Voltage Output 8-/10-/12-Bit DACs
FUNCTIONAL BLOCK DIAGRAMVOUT
VDD
SCL
GND
A1*
PD*
SDA
*AVAILABLE ON 8-LEAD VERSION ONLY
FEATURES
AD5301: Buffered Voltage Output 8-Bit DAC
AD5311: Buffered Voltage Output 10-Bit DAC
AD5321: Buffered Voltage Output 12-Bit DAC
6-Lead SOT-23 and 8-Lead mSOIC Packages
Micropower Operation: 120 mA @ 3 V
2-Wire (I2C® Compatible) Serial Interface
Data Readback Capability
+2.5 V to +5.5 V Power Supply
Guaranteed Monotonic By Design Over All Codes
Power-Down to 50 nA @ 3 V
Reference Derived from Power Supply
Power-On-Reset to Zero Volts
On-Chip Rail-to-Rail Output Buffer Amplifier
Three Power-Down Functions
APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
GENERAL DESCRIPTION
The AD5301/AD5311/AD5321 are single 8-, 10- and 12-bit
buffered voltage-output DACs that operate from a single +2.5 V
to +5.5 V supply consuming 120 mA at 3 V. The on-chip output
amplifier allows rail-to-rail output swing with a slew rate of
0.7 V/ms. It uses a 2-wire (I2C compatible) serial interface that
operates at clock rates up to 400 kHz. Multiple devices can
share the same bus.
The reference for the DAC is derived from the power supply
inputs and thus gives the widest dynamic output range. These
parts incorporate a power-on-reset circuit, which ensures that
the DAC output powers-up to zero volts and remains there until
a valid write takes place. The parts contain a power-down feature
which reduces the current consumption of the device to 50 nA
at 3 V and provides software-selectable output loads while in
power-down mode.
The low power consumption in normal operation make these
DACs ideally suited to portable battery-operated equipment.
The power consumption is 0.75 mW at 5 V, 0.36 mW at 3 V
reducing to 1 mW in all power-down modes.2C is a registered trademark of Philips Corporation.
*. Patent No. 5684481, other patent pending.
AD5301/AD5311/AD5321–SPECIFICATIONS(VDD = +2.5 V to +5.5 V; RL = 2 kV to GND;
CL = 200 pF to GND; All specifications TMIN to TMAX unless otherwise noted.)
NOTESSee Terminology.
2Temperature ranges are as follows: B Version: –40°C to +105°C.DC specifications tested with the outputs unloaded.
AC CHARACTERISTICS1
Output Voltage Settling Time
Slew Rate
Major-Code Change Glitch Impulse
NOTESSee TerminologyGuaranteed by design and characterization, not production tested.Temperature ranges are as follows: B Version: –40°C to +105°C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1
t11
NOTESSee Figure 1.Guaranteed by design and characterization, not production tested.A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH MIN of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.
Specifications subject to change without notice.
(VDD = +2.5 V to +5.5 V; RL = 2 kW to GND; CL = 200 pF to GND; All specifications TMIN to TMAX unless
otherwise noted.)
(VDD = +2.5 V to +5.5 V. All specifications TMIN to TMAX unless otherwise noted.)
AD5301/AD5311/AD5321
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5301/AD5311/AD5321 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
SCL, SDA to GND . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 VPD, A1, A0 to GND . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
VOUT to GND . . . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . .–40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . .+150°C
SOT-23 Package
Power Dissipation . . . . . . . . . . . . . . . . . . .(TJ max – TA)/qJAqJA Thermal Impedance . . . . . . . . . . . . . . . . . . . .229.6°C/W
ORDERING GUIDE
AD5301BRMSOIC Package
Power Dissipation . . . . . . . . . . . . . . . . . . .(TJ max – TA)/qJAqJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .206°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.t10
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
SDA
SCL
Figure 1.2-Wire Serial Interface Timing Diagram
PIN CONFIGURATIONS
6-Lead SOT-238-Lead mSOIC
(RT-6)(RM-8)
PIN FUNCTION DESCRIPTION
AD5301/AD5311/AD5321
TERMINOLOGY
RELATIVE ACCURACY
For the DAC, Relative Accuracy or Integral Nonlinearity (INL)
is a measure of the maximum deviation, in LSBs, from a straight
line passing through the actual endpoints of the DAC transfer
function. Typical INL vs. Code plots can be seen in Figures 2
to 4.
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of –1 LSB
maximum ensures monotonicity. These DACs are guaranteed
monotonic by design over all codes. Typical DNL vs. Code
plots can be seen in Figures 5 to 7.
ZERO CODE ERROR
Zero Code Error is a measure of the output error when zero
code (00H) is loaded to the DAC register. Ideally, the output
should be 0 V. The Zero Code Error of the AD5301/AD5311/
AD5321 is always positive because the output of the DAC can-
not go below 0 V. It is due to a combination of the offset errors
in the DAC and output amplifier. It is expressed in mV, see
Figure 9.
FULL-SCALE ERROR
Full-Scale Error is a measure of the output error when full scale
is loaded to the DAC register. Ideally, the output should be VDD
– 1 LSB. Full-scale error is expressed in percent of FSR (full-
scale range). A plot can be seen in Figure 9.
GAIN ERROR
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.
ZERO CODE ERROR DRIFT
This is a measure of the change in zero code error with a
change in temperature. It is expressed in mV/°C.
GAIN ERROR DRIFT
This is a measure of the change in gain error with changes in tem-
perature. It is expressed in (ppm of full-scale range)/°C.
MAJOR CODE TRANSITION GLITCH ENERGY
Major Code Transition Glitch Energy is the energy of the im-
pulse injected into the analog output when the code in the DAC
register changes state. It is normally specified as the area of the
glitch in nV-secs and is measured when the digital code is
changed by 1 LSB at the major carry transition (011...11 to
100...00 or 100...00 to 011...11).
DIGITAL FEEDTHROUGH
Digital Feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital input pins of the
device but is measured when the DAC is not being written to. It
is specified in nV-secs and is measured with a full-scale change
on the digital input pins, i.e., from all 0s to all 1s and vice versa.
CODE
INL ERROR – LSBs
–0.5
Figure 2.AD5301 Typical INL Plot
CODE
DNL ERROR – LSBs
0.1
Figure 5.AD5301 Typical DNL Plot
TEMPERATURE – 8C
ERROR – LSBs
0.25
Figure 8.AD5301 INL Error and
DNL Error vs. Temperature
CODE
INL ERROR – LSBs2001000400600800
Figure 3.AD5311 Typical INL Plot
CODE
DNL ERROR – LSBs
–0.4
Figure 6.AD5311 Typical DNL Plot
TEMPERATURE – 8C
ERROR –
–106020–20
Figure 9.Zero-Code Error and Full-
Scale Error vs. Temperature

Figure 4.AD5321 Typical INL Plot
CODE
DNL ERROR – LSBs
–0.5
Figure 7.AD5321 Typical DNL Plot

Figure 10.IDD Histogram with VDD =
+3 V and VDD = +5 V
AD5301/AD5311/AD5321

I – mA
OUT
– V036
912
Figure 11. Source and Sink Current
Capability
VDD – Volts
–
Figure 14. Power-Down Current vs.
Supply Voltage␣

CH1 1V, CH2 1V, TIME BASE = 20ms/DIV
CH2
CH1
Figure 17. Power-On Reset to 0 V
–
ZERO-SCALEFULL-SCALE
CODE
Figure 12.Supply Current vs. Code
V – Volts
IDD
–
1.02.03.04.05.0
Figure 15.Supply Current vs. Logic
Input Voltage for SDA and SCL Volt-
age Increasing and Decreasing
CH1 1V, CH2 5V, TIME BASE = 1ms/DIV
CH2
CH1
Figure 18.Exiting Power-Down to
Midscale

Figure 13.Supply Current vs. Supply
Voltage

Figure 16.Half-Scale Settling (1/4 to
3/4 Scale Code Charge)
Figure 19.Major-Code Transition

Partno	Mfg	Dc	Qty	Available	Descript
AD5311BRM	AD	N/a	13164	avai	+2.5 V to +5.5 V, 120 uA, 2-Wire Interface, Voltage Output 8-/10-/12-Bit DACs
AD5321BRM	AD	N/a	1011	avai	+2.5 V to +5.5 V, 120 uA, 2-Wire Interface, Voltage Output 8-/10-/12-Bit DACs
AD5301BRM	AD	N/a	576	avai	+2.5 V to +5.5 V, 120 uA, 2-Wire Interface, Voltage Output 8-/10-/12-Bit DACs