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AD5290YRMZ10
Compact +30V/±15V 256-Position Digital Potentiometer
Compact +30V/±15V 256-Position Digital
Potentiometer
Rev. PrC
FEATURES
256-position
+2.7V to +30V Single Supply Operation
±2.7V to ±15V Dual Supply Operation
End-to-end resistance 10 kΩ, 50 kΩ, 100 kΩ
Low temperature coefficient 35 ppm/°C
Power-on preset to midscale
SPI compatible interface
Automotive temperature range –40°C to +105°C
Compact MSOP-10 (3 mm × 4.9 mm) package
APPLICATIONS
Programmable Gain and Offset
Programmable Power Supply
Industrial Actuator Control
LED Array Driver
Audio Volume Control
General Purpose DAC Replacement
Mechanical Potentiometer Replacement
GENERAL OVERVIEW The AD5290 is a low cost, compact 2.9 mm × 3 mm
+30V/±15V, 256-position digital potentiometer. This device
performs the same electronic adjustment function as
mechanical potentiometers or variable resistors, with enhanced
resolution, solid-state reliability, and superior low temperature
coefficient performance.
The wiper settings are controllable through an SPI compatible
digital interface. The resistance between the wiper and either
end point of the fixed resistor varies linearly with respect to the
digital code transferred into the RDAC latch.
The AD5290 is available in 10k, 50k, and 100kΩ in compact
MSOP-10 package. AD5290 can be operated from a single
supply +2.7 V to +30 V or dual supply ±2.7 V to ±15 V. All
parts are guaranteed to operate over the automotive
temperature range of -40°C to +105°C.
FUNCTIONAL BLOCK DIAGRAM Figure 1.
Note:
The terms digital potentiometer and RDAC are used interchangeably.
ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS (VDD/VSS = ±15V±10% or ±5V±10%, VA = +VDD, VB = VSS/0V, -40°C < TA < +105°C unless otherwise noted)
Table 1.
TIMING CHARACTERISTICS— 10 kΩ, 50 kΩ, 100 kΩ VERSIONS (VDD/VSS = ±15V±10% or ±5V±10%, VA = +VDD, VB = 0V, -40°C < TA < +105°C unless otherwise noted.)
Table 2. NOTES
1. Typical specifications represent average readings at +25°C and VDD = 5 V.
2. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3. VAB = VDD, Wiper (VW) = no connect.
4. INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA=VDD and VB=0 V.
5. Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6. Guaranteed by design and not subject to production test.
7. PDISS is calculated from (IDD × VDD+ ISS × VSS) CMOS logic level inputs result in minimum power dissipation.
8. All dynamic characteristics use VDD / VSS = ±5 V.
9. See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level
of 1.5 V.
ABSOLUTE MAXIMUM RATINGS1 (TA = +25°C, unless otherwise noted.)
Table 3. NOTES
1 Maximum terminal current is bounded by the maximum current handling
of the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Package power dissipation = (TJMAX – TA)/θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VSS
VDD
SDO
SDIGNDCLKCSFigure 2. AD5290 Pin Configuration
Table 7. AD5290 Pin Function Descriptions
