AD5280BRU20 ,+15V, I2C Compatible Digital PotentiometersSpecifications apply to all VRs Resolution N 8 Bits 4Integral Nonlinearity INL RAB=20KΩ , 50KΩ ..
AD5282BRU50 ,+15V, I2C Compatible Digital Potentiometersapplications, see completely programmable value of resistance, between the A AD5203/AD5204/AD5206/A ..
AD5290YRMZ10 ,Compact +30V/±15V 256-Position Digital PotentiometerCHARACTERISTICS—POTENTIOMETER DIVIDER MODE Resolution N 8 Bits 4 Differential Nonlinearity ..
AD5300BRM ,+2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 8-Bit DAC in an SOT-23Specifications subject to change without notice. t1SCLKt8t2tt3 7t4SYNCt6t5DB0DIN DB15Figure 1. Seri ..
AD5300BRT ,+2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 8-Bit DAC in an SOT-23applications.to 30 MHz and is compatible with standard SPI™, QSPI™,3. The on-chip output buffer amp ..
AD5300BRT ,+2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 8-Bit DAC in an SOT-23CHARACTERISTICSOutput Voltage Range 0 V VDDOutput Voltage Settling Time 4 6 m s 1/4 Scale to 3/4 Sc ..
AD9100AD ,Ultrahigh Speed Monolithic Track-and-HoldSpecifications subject to change without notice.–2– REV. BAD9100APERTURE+2VDELAY(0.8ns)ANALOG0VINPU ..
AD9100JD ,Ultrahigh Speed Monolithic Track-and-HoldCHARACTERISTICSS S LOAD IN1Test AD9100JD/AD/SDParameter Conditions Temp Level Min Typ Max Units ..
AD9119BBCZ , 11-/14-Bit, 5.6 GSPS, RF Digital-to-Analog Converter
AD9122BCPZRL , Dual, 16-Bit, 1200 MSPS, TxDAC® Digital-to-Analog Converter
AD9125BCPZ , Dual, 16-Bit, 1000 MSPS, TxDAC Digital-to-Analog Converter
AD9142BCPZ , Dual, 16-Bit, 1600 MSPS, TxDAC Digital-to-Analog Converter
AD5280BRU20-AD5282BRU50
+15V, I2C Compatible Digital Potentiometers
PRELIMINARY TECHNICAL DATA+15V, I2C Compatible Digital Potentiometers
FEATURES 256 Position
AD5280 – 1-Channel
AD5282 – 2-Channel (Independently Programmable)
Potentiometer Replacement
20K, 50K, 200K Ohm with TC < 50ppm/ºC
Internal Power ON Mid-Scale Preset
+5 to +15V Single-Supply; ±5.5V Dual-Supply Operation 2C Compatible Interface
APPLICATIONS Multi-Media, Video & Audio
Communications
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage to Current Conversion
Line Impedance Matching
GENERAL DESCRIPTION The AD5280/AD5282 provides a single/dual channel, 256 position
digitally-controlled variable resistor (VR) device. These devices
perform the same electronic adjustment function as a
potentiometer, trimmer or variable resistor. Each VR offers a
completely programmable value of resistance, between the A
terminal and the wiper, or the B terminal and the wiper. The fixed
A-to-B terminal resistance of 20, 50 or 200K ohms has a 1%
channel-to-channel matching tolerance with a nominal temperature
coefficient of 30 ppm/°C.
Wiper Position programming defaults to midscale at system power
ON. Once powered the VR wiper position is programmed by a I2C
compatible 2-wire serial data interface. Both parts have two
programmable logic outputs available to drive digital loads, gates,
LED drivers, analog switches, etc.
FUNCTIONAL BLOCK DIAGRAMS
SDA
SCL
VSS
VDD
GNDW1B1
SHDN
AD0AD1
SDA
SCL
VSS
VDD
GNDW1B1
SHDNW2B2
AD0AD1The AD5280/AD5282 are available in ultra compact surface mount
thin TSSOP-14/-16 packages. All parts are guaranteed to operate
over the extended industrial temperature range of -40°C to +85°C.
For 3-wire, SPI compatible interface applications, see
AD5203/AD5204/AD5206/AD7376/AD8400/AD8402/AD8403/
AD5260/AD5262/AD5200/AD5201 products.
ORDERING GUIDE The AD5280/AD5282 die size is 75 mil X 120 mil, 9,000 sq. mil.
Contains xxx transistors. Patent Number xxx applies.
PRELIMINARY TECHNICAL DATAAD5280/AD5282
ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION (VDD = +5V, VSS = -5V, VLOGIC = +5V, VA = +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)
Parameter Symbol Conditions Min Typ1 Max Units
PRELIMINARY TECHNICAL DATAAD5280/AD5282
ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION (VDD = +5V, VSS = -5V, VLOGIC = +5V,
VA = +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.) Parameter Symbol Conditions Min Typ1 Max Units
NOTES:
1. Typicals represent average readings at +25°C, VDD = +5V, VSS = -5V.
2. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the
relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3. VAB = VDD, Wiper (VW) = No connect
4. INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V. DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions.
5. Resistor terminals A,B,W have no limitations on polarity with respect to each other.
6. Guaranteed by design and not subject to production test.
9. Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value
result in the minimum overall power consumption.
10. PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation.
11. All dynamic characteristics use VDD = +5V.
12. See timing diagram for location of measured values.
PRELIMINARY TECHNICAL DATAAD5280/AD5282
ABSOLUTE MAXIMUM RATINGS (TA = +25°C, unless
otherwise noted)
VDD to GND.............................................................-0.3, +15V
VSS to GND..................................................................0V, -7V
VDD to VSS ...................................................................... +15V
VA, VB, VW to GND...................................................VSS, VDD
AX – BX, AX – WX, BX – WX.........................................±20mA
Digital Input Voltage to GND.........................................0V, 7V
Operating Temperature Range...........................-40°C to +85°C
Thermal Resistance* θJA,
TSSOP-14........................................................206°C/W
TSSOP-16........................................................180°C/W
Maximum Junction Temperature (TJ MAX)....................+150°C
Storage Temperature........................................-65°C to +150°C
Lead Temperature RU-14, RU-16 (Vapor Phase, 60 sec) .......................+215°C RU-14, RU-16 (Infrared, 15 sec) ..............................+220°C Package Power Dissipation (TJMAX - TA) / θJA
AD5280 PIN CONFIGURATION A
VDD
SCL
SDA
O1
VL
O2
VSS
GND
AD1
AD0
AD5282 PIN CONFIGURATION
O1
A1
W1
B1
VDD
SCL
SDA
A2
W2
B2
VL
VSS
GND
AD1
AD0
TABLE 1: AD5280 PIN Function Descriptions
Pin Name Description A Resistor terminal A W Wiper terminal W B Resistor terminal B
4 VDD Positive power supply, specified for
operation from +5 to +15V. SHDN Active Low, Asynchronous connection of
the wiper W to terminal B, and open
circuit of terminal A. RDAC register
contents unchanged. SCL Serial Clock Input SDA Serial Data Input/Output AD0 Programmable address bit for multiple
package decoding. Bits AD0 & AD1
provide 4 possible addresses. AD1 Programmable address bit for multiple
package decoding. Bits AD0 & AD1
provide 4 possible addresses.
10 GND Common Ground
11 VSS Negative power supply, specified for
operation from 0 to -5V
12 O2 Logic Output terminal O2
13 VL Logic Supply Voltage, needs to be same
voltage as the digital logic controlling the
AD5280.
14 O1 Logic Output terminal O1
PRELIMINARY TECHNICAL DATAAD5280/AD5282
TABLE 2: AD5282 PIN Function Descriptions
Pin Name Description O1 Logic Output terminal O1
2 A1 Resistor terminal A1
3 W1 Wiper terminal W1
4 B1 Resistor terminal B1
5 VDD Positive power supply, specified for
operation from +5 to +15V. SHDN Active Low, Asynchronous connection of
the wiper W to terminal B, and open
circuit of terminal A. RDAC register
contents unchanged. SCL Serial Clock Input SDA Serial Data Input/Output AD0 Programmable address bit for multiple
package decoding. Bits AD0 & AD1
provide 4 possible addresses.
10 AD1 Programmable address bit for multiple
package decoding. Bits AD0 & AD1
provide 4 possible addresses.
11 GND Common Ground
12 VSS Negative power supply, specified for
operation from 0 to -5V
13 VL Logic Supply Voltage, needs to be same
voltage as the digital logic controlling the
AD5282.
14 B2 Resistor terminal B2
15 W2 Wiper terminal W2
16 A2 Resistor terminal A2 4
SDA
SCLt3t578910Figure 1. Detail Timing Diagram
Data of AD5280/AD5282 is accepted from the I2C bus in the following serial format:
Where:
S = Start Condition
P = Stop Condition
A = Acknowledge
X = Don’t Care
AD1, AD0 = Package pin programmable address bits
R/WWWW= Read Enable at High and Write Enable at Low AAA/B = RDAC sub address select. “Zero” for RDAC1 and “One” for RDAC2
SD = Shutdown, same as SHDN pin operation except inverse logic
O2, O1 = Output logic pin latched values
D7,D6,D5,D4,D3,D2,D1,D0 = Data Bits
SCL
SDA90110AD0AD1R/W
ACK.BYAD5280D6D5D3D4D0D1D29
ACK.BYAD5280
A/BRSSDO2O1XXX9
ACK.BYAD5280
FRAME1SlaveAddressByte
STARTBYMASTERFRAME2InstructionByteFRAME3DataByte
Figure 2. Writing to the RDAC Register
PRELIMINARY TECHNICAL DATAAD5280/AD5282 9
ACK.BYACK.BYMASTER
FRAME1SlaveAddressByte
STARTBYMASTERFRAME2DataFromSelected
STOPBYMASTER
Figure 3. Reading Data from a Previously Selected RDAC Register
OPERATION
The AD5280/AD5282 provides a single/dual channel, 256-
position digitally-controlled variable resistor (VR) device. The
terms VR and RDAC are used interchangeably throughout this
documentation. To program the VR settings, refer to the Digital
Interface section. Both parts have an internal power ON preset
that places the wiper in mid scale during power on, which
simplifies the fault condition recovery at power up. In addition,
the shutdown SHDN pin of AD5280/AD5282 places the RDAC
in a zero power consumption state where terminal A is open
circuited and the wiper W is connected to terminal B, resulting
in only leakage currents being consumed in the VR structure. In
shutdown mode the VR latch settings are maintained, so that,
returning to operational mode from power shutdown, the VR
settings return to their previous resistance values.
SHDNFigure 4. AD5280/AD5282 Equivalent RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between terminals A and B
are available in 20KΩ, 50KΩ, and 200KΩ. The final three
digits of the part number determine the nominal resistance
value, e.g. 20KΩ = 20; 50KΩ = 50; 200KΩ = 200. The
nominal resistance (RAB) of the VR has 256 contact points
accessed by the wiper terminal, plus the B terminal contact. The
eight bit data in the RDAC latch is decoded to select one of the
256 possible settings. Assume a 20KΩ part is used, the wiper's
first connection starts at the B terminal for data 00H. Since there
is a 60Ω wiper contact resistance, such connection yields a
minimum of 60Ω resistance between terminals W and B. The
second connection is the first tap point corresponds to 138Ω
(RWB = RAB/256 + RW = 78Ω+60Ω) for data 01H. The third
for data 02H and so on. Each LSB data value increase moves the
wiper up the resistor ladder until the last tap point is reached at
19982Ω [RAB–1LSB+RW]. The wiper does not directly connect
to the B terminal. See Figure 4 for a simplified diagram of the
equivalent RDAC circuit.
The general equation determining the digitally programmed
output resistance between W and B is: eqn. 256)(WABWBRRDDR+⋅=
where D is the decimal equivalent of the binary code which is
loaded in the 8-bit RDAC register, and RAB is the nominal end-
to-end resistance.
For example, RAB=20KΩ, when VB = 0V and A–terminal is open
circuit, the following output resistance values RWB will be set for
the following RDAC latch codes. Result will be the same if
terminal A is tied to W:
D RWB Output State
Note that in the zero-scale condition a finite wiper resistance of
60Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum current of no more
than 5mA. Otherwise, degradation or possible destruction of the
internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
digitally controlled resistance RWA. When these terminals are
used the B–terminal should be let open or tied to the wiper
terminal. Setting the resistance value for RWA starts at a
maximum value of resistance and decreases as the data loaded in
the latch is increased in value. The general equation for this
operation is: eqn. 256
256)(WABWARRDDR+⋅−=
