AD5263BRU20 Fast Delivery |IC PHOENIX CO.,LIMITED

AD5263BRU20 ,+15 V, Quad, 256 Position, Digital PotentiometerSpecifications apply to all VRs.) Resolution N 8 Bits 4 Differential Nonlinearity DNL –1 ± ..
AD526AD ,Software Programmable Gain AmplifierSpecifications subject to change without notice.
AD526AD ,Software Programmable Gain AmplifierFEATURES PIN CONFIGURATIONDigitally Programmable Binary Gains from 1 to 16Two-Chip Cascade Mode Ach ..
AD526BD ,Software Programmable Gain AmplifierSpecifications shown in boldface are tested on all production units at final electrical test. All m ..
AD526CD ,Software Programmable Gain Amplifierapplications requiring programmable Additional gains of 32, 64, 128 and 256 are possible by cas-gai ..
AD526JN ,Software Programmable Gain Amplifierspecifications.+125

AD5263BRU20
+15 V, Quad, 256 Position, Digital Potentiometer
Quad, 15 V, 256-Position, Digital
Potentiometer with Pin Selectable SPI/I2C
Rev. 0
FEATURES
256-position, 4-channel
End-to-end resistance 20 kΩ, 50 kΩ, 200 kΩ
Pin selectable SPI® or I2C® compatible interface
Power-on preset to midscale
Two package address decode pins AD0 and AD1
Rheostat mode temperature coefficient 30 ppm/°C
Voltage divider temperature coefficient 5 ppm/°C
Wide operating temperature range –40°C to +125°C
5 V to 15 V single supply; ±5 V dual supply
APPLICATIONS
Mechanical potentiometer replacement
Optical network adjustment
Instrumentation: gain, offset adjustment
Stereo channel audio level control
Automotive electronics adjustment
Programmable power supply
Programmable filters, delays, time constants
Line impedance matching
Low resolution DAC/trimmer replacement
Base station power amp biasing
Sensor calibration
GENERAL DESCRIPTION
The AD5263 is the industry’s first quad-channel, 256-position,
digital potentiometer1 with a selectable digital interface. This
device performs the same electronic adjustment function as
mechanical potentiometers or variable resistors, with enhanced
resolution, solid-state reliability, and superior low temperature
coefficient performance.
Each channel of the AD5263 offers a completely programmable
value of resistance between the A terminal and the wiper, or
between the B terminal and the wiper. The fixed A-to-B
terminal resistance of 20 kΩ, 50 kΩ, or 200 kΩ has a nominal
temperature coefficient of ±30 ppm/°C and a ±1% channel-to-
channel matching tolerance. Another key feature of this part is
the ability to operate from +4.5 V to +15 V, or at ±5 V.
Wiper position programming presets to midscale upon power-
on. Once powered, the VR wiper position is programmed by
either the 3-wire SPI or 2-wire I2C compatible interface. In the 2C mode, additional programmable logic outputs enable users
to drive digital loads, logic gates, and analog switches in their
systems.
The AD5263 is available in a narrow body TSSOP-24. All parts
are guaranteed to operate over the automotive temperature
range of –40°C to +125°C.
For single- or dual-channel applications, refer to the
AD5260/AD5280 or AD5262/AD5282.
FUNCTIONAL BLOCK DIAGRAM
GNDW1B1A2W2B2A3W3B3A4W4B4
CS/AD0
SDI/SDA
CLK/SCL
VDD
VSS
SHDN
RES/AD1
DISNC/O2SDO/O1
Figure 1.
The terms digital potentiometer, VR, and RDAC are used interchangeably.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed
Associated Companies conveys a license for the purchaser under the Philips I2C
Patent Rights to use these components in an I2C system, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
TABLE OF CONTENTS
Electrical Characteristics—20 kΩ, 50 kΩ, 200 kΩ Versions.......3
Timing Characteristics—20 kΩ, 50 kΩ, 200 kΩ Versions...........4
Absolute Maximum Ratings............................................................5
Typical Performance Characteristics.............................................6
Test Circuits.....................................................................................11
SPI Compatible Digital Interface (DIS = 0)................................12 2C Compatible Digital Interface (DIS = 1).................................13
Operation.........................................................................................14
Programming the Variable Resistor.........................................14
Programming the Potentiometer Divider...............................15
Pin Selectable Digital Interface.................................................15
SPI Compatible 3-Wire Serial Bus (DIS = 0)..........................15 2C Compatible 2-Wire Serial Bus (DIS = 1)..........................16
Additional Programmable Logic Output................................17
Self-Contained Shutdown Function........................................17
Multiple Devices on One Bus...................................................17
Level Shift for Negative Voltage Operation.............................17
ESD Protection...........................................................................18
Terminal Voltage Operating Range..........................................18
Power-Up Sequence...................................................................18
VLOGIC Power Supply...................................................................18
Layout and Power Supply Bypassing.......................................18
RDAC Circuit Simulation Model.............................................19
Applications.....................................................................................20
Bipolar DC or AC Operation from Dual Supplies.................20
Gain Control Compensation....................................................20
Programmable Voltage Reference............................................20
8-Bit Bipolar DAC......................................................................21
Bipolar Programmable Gain Amplifier...................................21
Programmable Voltage Source with Boosted Output............21
Programmable 4–20 mA Current Source...............................22
Programmable Bidirectional Current Source.........................22
Programmable Low-Pass Filter................................................23
Programmable Oscillator..........................................................23
Resistance Scaling......................................................................24
Resistance Tolerance, Drift, and Temperature Coefficient
Mismatch Considerations.........................................................24
Pin Configuration and Pin Function Descriptions....................25
Pin Configuration......................................................................25
Pin Function Descriptions........................................................25
Outline Dimensions.......................................................................26
ESD Caution................................................................................26
Ordering Guide...............................................................................26
REVISION HISTORY
Revision 0: Initial Version
ELECTRICAL CHARACTERISTICS—20 kΩ, 50 kΩ, 200 kΩ VERSIONS
(VDD = +5 V, VSS = –5 V, VL = +5 V, VA = +VDD, VB = 0 V, –40°C < TA < +125°C, unless otherwise noted.)
Table 1.
TIMING CHARACTERISTICS—20 kΩ, 50 kΩ, 200 kΩ VERSIONS
(VDD = +5 V, VSS = –5 V, VL = +5 V, VA = +VDD, VB = 0 V, –40°C < TA < +125°C unless otherwise noted.)
Table 2.
NOTES
1 Typicals represent average readings at 25°C and VDD = +5 V, VSS = –5 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD = +5 V and
VSS = –5 V.
3 VAB = VDD, Wiper (VW) = no connect. INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test. Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
8 VL is limited to VDD or 5.5 V, whichever is less. Worst-case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic.
10 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. All dynamic characteristics use VDD = +5 V, VSS = –5 V, VL = +5 V.
12 Settling time depends on value of VDD, RL, and CL. See timing diagrams for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level
of 1.5 V. Switching characteristics are measured using VL = +5 V.
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C, unless otherwise noted.)
Table 3.
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Package power dissipation: (TJMAX – TA)/θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
TYPICAL PERFORMANCE CHARACTERISTICS
(RAB = 20 kΩ unless otherwise noted.)
RHE
TAT MODE
DNL (LS
CODE (Decimal)
0.6
Figure 2. R-DNL vs. Code vs. Supply Voltage
RHEOSTAT MODE INL (LSB)
CODE (Decimal)
0.6
Figure 3. R-INL vs. Code vs. Supply Voltage
RHE
TAT MODE
DNL (LS
CODE (Decimal)
0.6
Figure 4. R-DNL vs. Code; VDD = ±5 V
RHEOSTAT MODE INL (LSB)
CODE (Decimal)
0.6
Figure 5. R-INL vs. Code; VDD = ±5 V
NTIOME
R MODE
INL (LS
CODE (Decimal)
0.6
Figure 6. INL vs. Code vs. Supply Voltage
NTIOME
R MODE
DNL (LS
CODE (Decimal)
0.6
Figure 7. DNL vs. Code vs. Supply Voltage
NTIOME
R MODE
INL (LS
CODE (Decimal)
0.6
Figure 8. INL vs. Code; VDD = ±5 V
NTIOME
R MODE
DNL (LS
CODE (Decimal)
0.6
Figure 9. DNL vs. Code; VDD = ±5 V
FSE (
TEMPERATURE (°C)
03142-0-009
Figure 10. Full-Scale Error vs. Temperature
ZSE (
TEMPERATURE (°C)
03142-0-010
Figure 11. Zero-Scale Error vs. Temperature
IDD
CURRE
TEMPERATURE (°C)
TEMPERATURE (°C)80–4012040
03142-0-011
Figure 12. Supply Current vs. Temperature
HUTDOWN CURRE
NT (
TEMPERATURE (°C)
03142-0-012
Figure 13. Shutdown Current vs. Temperature
LOGIC
TEMPERATURE (°C)80–4012040
03142-0-013
Figure 14. ILOGIC vs. Temperature
WIP
RE
ANCE
VBIAS (V)
03142-0-014
Figure 15. Wiper ON Resistance vs. Bias Voltage
RHEOSTAT MODE TEMPCO (ppm/°
CODE (Decimal)
160192224256
Figure 16. Rheostat Mode Tempco ∆RWB/∆T vs. Code
NTIOME
MODE
TE
CO (ppm/
CODE (Decimal)
150
Figure 17. Potentiometer Mode Tempco ∆RWB/∆T vs. Code
GAIN (
FREQUENCY(Hz)
Figure 18. Gain vs. Frequency vs. Code; RAB = 20 kΩ
GAIN (
FREQUENCY(Hz)
Figure 19. Gain vs. Frequency vs. Code; RAB = 50 kΩ
GAIN (
FREQUENCY (Hz)
03142-0-019
Figure 20. Gain vs. Frequency vs. Code; RAB = 200 kΩ
(d
FREQUENCY (Hz)
Figure 21. –3 db Bandwidth
PSRR (
dB)
FREQUENCY (Hz)
03142-0-021
Figure 22. PSRR vs. Frequency
Figure 23. Digital Feedthrough
Figure 24. Midscale Glitch; Code 0x80–ox7F
(4.7 nF Capacitor Used from Wiper to Ground)
Figure 25. Large Signal Settling Time; Code 0x00–0xFF
INL (
SB)
|VDD– VSS| (–V)
03142-0-025
Figure 26. INL vs. Supply Voltage
R-INL (LS
|VDD– VSS| (V)5
03142-0-026
Figure 27. R-INL vs. Supply Voltage
TEST CIRCUITS
Figure 28 to Figure 38 define the test conditions used in the
product specification table.
V+= VDD
1LSB = V+/2N
Figure 28. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
NO CONNECT
Figure 29. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
VMS2= [VMS1– VMS2]/IW
Figure 30. Test Circuit for Wiper Resistance
03142-0-031
∆VMS%
DD%PSS (%/%) = = VDD10%
PSRR (dB) = 20 LOGMS( )∆V
Figure 31. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
VOUTOFFSETGNDOFFSETDUT
Figure 32. Test Circuit for Inverting Gain
OFFSETGND
+15V
2.5VOFFSETGND
VIN
Figure 34. Test Circuit for Gain vs Frequency
VSS TO VDD
DUT
RSW=0.1V
ISW
0.1V
Figure 35. Test Circuit for Incremental ON Resistance
03142-0-036
Figure 36. Test Circuit for Common Mode Leakage Current
VLOGIC
SCL
SCA
ILOGIC
Figure 37. Test Circuit for VLOGIC Current vs. Digital Input Voltage
VIN
VOUT
CTA = 20 log[VOUT/VIN]
Figure 38. Test Circuit for Analog Crosstalk
SPI COMPATIBLE DIGITAL INTERFACE (DIS = 0)
Table 4. AD5263 Serial Data-Word Format
SDI
CLK
Figure 39. AD5263 Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT)
SDI
CLK
VOUT
VDD
(DATA IN)
tCH
Figure 40. Detailed SPI Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT)
2C COMPATIBLE DIGITAL INTERFACE (DIS = 1) Table 5. I2C Write Mode Data-Word Format
Table 6. I2C Read Mode Data-Word Format
S = Start condition.
P = Stop condition.
A = Acknowledge.
AD1, AD0 = I2C device address bits. Must match with the logic
states at pins AD1, AD0. Refer to Figure 48.
A1, A0 = RDAC channel select.
RS = Software reset wiper (A1, A0) to midscale position.
SD = Shutdown active high; ties wiper (A1, A0) to Terminal A,
opens Terminal B, RDAC register contents are not disturbed. To
exit shutdown, the command SD = 0 must be executed for each
RDAC (A1, A0).
O1, O2 = Data to digital output pins O1, O2 in I2C mode, used
to drive external logic. The logic high level is determined by VL
and the logic low level is GND.
W = Write = 0.
R = Read = 1.
D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits.
X = Don’t Care.
SCLPS
Figure 41. Detailed I2C Timing Diagram
FRAME 1FRAME 2START BYMASTER
ACK BYAD5263
SLAVE ADDRESS BYTESTOP BYMASTERINSTRUCTION BYTE
SDA919
ACK BYAD5263FRAME 3DATA BYTE9
ACK BYAD5263
Figure 42. Writing to the RDAC Register
NO ACKBY MASTER919
FRAME 1FRAME 2START BY
ACK BYAD5263
SLAVE ADDRESS BYTERDAC REGISTERSTOP BY
OPERATION
The AD5263 is a quad-channel, 256-position, digitally
controlled, variable resistor (VR) device.
To program the VR settings, refer to the interface sections of the
previous pages. The part has an internal power-on preset that
places the wiper at midscale during power-on, which simplifies
the fault condition recovery at power-up. In addition, the shut-
down SHDN pin of AD5263 places the RDAC in an almost zero
power consumption state where Terminal A is open circuited
and the wiper W is connected to Terminal B, resulting in only
leakage current consumption in the VR structure. During shut-
down, the VR latch settings are maintained or new settings can
be programmed. When the part is returned from shutdown, the
corresponding VR setting will be applied to the RDAC.
SD BITRS
Figure 44. AD5263 Equivalent RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between Terminals A and
B is available in 20 kΩ, 50 kΩ, and 200 kΩ. The final two or
three digits of the part number determine the nominal
resistance value, e.g., 20 kΩ = 20; 50 kΩ = 50; 200 kΩ = 200. The
nominal resistance (RAB) of the VR has 256 contact points
accessed by the wiper terminal, plus the B terminal contact. The
8-bit data in the RDAC latch is decoded to select one of the 256
possible settings. Assuming a 20 kΩ part is used, the wiper's first
connection starts at the B terminal for data 0x00. Since there is a
60 Ω wiper contact resistance, such a connection yields a
minimum of 2 × 60 Ω resistance between Terminals W and B.
The second connection is the first tap point, and corresponds to
198 Ω (RWB = RAB/256 + RW = 78 Ω + 2 × 60 Ω) for data 0x01.
The third connection is the next tap point representing 216 Ω
(RWB = 78 Ω × 2 + 2 × 60 Ω) for data 0x02, and so on. Each LSB
data value increase moves the wiper up the resistor ladder until
the last tap point is reached at 19,982 Ω (RAB – 1 LSB + 2 × RW).
Figure 44 shows a simplified diagram of the equivalent RDAC
therefore, there is 1 LSB less of the nominal resistance at full
scale in addition to the wiper resistance.
The general equation determining the digitally programmed
output resistance between Terminals W and B is ABWBRRDDR×+×=2256)( (1)
where:
D is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the ON resistance of
one internal switch.
In summary, if RAB = 20 kΩ and the A terminal is open-
circuited, the following RDAC latch codes result in the
corresponding output resistance, RWB.
Table 7. Codes and Corresponding RWB Resistances
Note that in the zero-scale condition a finite wiper resistance of
120 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and Terminal A also produces a
digitally controlled complementary resistance, RWA. When these
terminals are used, the B terminal can be opened. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is ABWARRDDR×+×=2256
256)( (2)
For RAB = 20 kΩ and the B terminal open-circuited, the
following RDAC latch codes result in the corresponding output
resistance RWA:
Table 8. Codes and Corresponding RWA Resistances

Partno	Mfg	Dc	Qty	Available	Descript
AD5263BRU20	AD	N/a	3	avai	+15 V, Quad, 256 Position, Digital Potentiometer