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AD5252 ,I2C, Nonvolatile Memory, Dual 256-Position Digital Potentiometerapplications. table, or system identification information. 2The AD5251/AD5252 are available in TSS ..
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AD5252BRUZ1 ,I2C, Nonvolatile Memory, Dual 256-Position Digital PotentiometerGENERAL DESCRIPTION 2The AD5251/AD5252 provide additional increment, The AD5251/AD5252 are dual-cha ..
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AD9057BRS-40 ,8-Bit 40 MSPS/50 MSPS/80 MSPS ConverterSPECIFICATIONSD DDTest AD9057BRS-40 AD9057BRS-60 AD9057BRS-80Parameter Temp Level Min Typ Max ..
AD9057BRS-60 ,8-Bit 40 MSPS/60 MSPS/80 MSPS A/D ConverterSPECIFICATIONSD DDTest AD9057BRS-40 AD9057BRS-60 AD9057BRS-80Parameter Temp Level Min Typ Max ..
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AD9058AJD ,Dual 8-Bit 50 MSPS A/D Converterapplications in which +V may be applied before –V , or +V current is not limited to 500 mA, a rever ..
AD9058AJJ ,Dual 8-Bit 50 MSPS A/D ConverterGENERAL DESCRIPTION CONVERTERAINThe AD9058 combines two independent, high performance,8-bit analog- ..
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AD5251BRU100-AD5251BRU50-AD5252-AD5252BRU1-RL7-AD5252BRUZ1
I2C, Nonvolatile Memory, Dual 64-Position Digital Potentiometer
Dual 64-and 256-Position I2C Nonvolatile
Memory Digital Potentiometers
Rev. 0
FEATURES
AD5251: Dual 64-position resolution
AD5252: Dual 256-position resolution
1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Nonvolatile memory1 stores wiper setting w/write protection
Power-on refreshed with EEMEM settings in 300 µs typ
EEMEM rewrite time = 540 µs typ
Resistance tolerance stored in nonvolatile memory
12 extra bytes in EEMEM for user-defined information 2C compatible serial interface
Direct read/write access of RDAC2 and EEMEM registers
Predefined linear increment/decrement commands
Predefined ±6 dB step change commands
Synchronous or aysynchronous dual channel update
Wiper setting read back
4 MHz bandwidth—1 kΩ version
Single supply 2.7 V to 5.5 V
Dual supply ±2.25 V to ±2.75 V
2 slave address decoding bits allow operation of 4 devices
100-year typical data retention TA = 55°C
Operating temperature –40°C to +85°C
APPLICATIONS
Mechanical potentiometer replacement
General purpose DAC replacement
LCD panel VCOM adjustment
White LED brightness adjustment
RF base station power amp bias control
Programmable gain and offset control
Programmable voltage-to-current conversion
Programmable power supply
Sensor calibrations
FUNDAMENTAL BLOCK DIAGRAM
VDD
VSS
DGND
SCL
SDA
AD0
AD1Figure 1.
The terms nonvolatile memory and EEMEM are used interchangeably.
2The terms digital potentiometer and RDAC are used interchangeably.
GENERAL DESCRIPTION The AD5251/AD5252 are dual-channel, I2C, nonvolatile mem-
ory, digitally controlled potentiometers with 64/256 positions,
respectively. These devices perform the same electronic adjust-
ment functions as mechanical potentiometers, trimmers, and
variable resistors. The parts’ versatile programmability allows
multiple modes of operation, including read/write access in the
RDAC and EEMEM registers, increment/decrement of
resistance, resistance changes in ±6 dB scales, wiper setting
readback, and extra EEMEM for storing user-defined infor-
mation such as memory data for other components, look-up
table, or system identification information.
The AD5251/AD5252 allow the host I2C controllers to write
any of the 64- or 256-step wiper settings in the RDAC registers
and store them in the EEMEM. Once the settings are stored,
they are restored automatically to the RDAC registers at system
power-on; the settings can also be restored dynamically.
The AD5251/AD5252 provide additional increment,
decrement, +6 dB step change, and –6 dB step change in
synchronous or asynchronous channel update modes. The
increment and decrement functions allow stepwise linear
adjustments, while ±6 dB step changes are equivalent to
doubling or halving the RDAC wiper setting. These functions
are useful for steep-slope nonlinear adjustments such as white
LED brightness and audio volume control. The parts have a
patented resistance tolerance storing function which enable the
user to access the EEMEM and obtain the absolute end-to-end
resistance values of the RDACs for precision applications.
The AD5251/AD5252 are available in TSSOP-14 packages in
1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ options and all parts can
operate over the –40°C to +85°C extended industrial
temperature range.
TABLE OF CONTENTS Electrical Characteristics.................................................................3
Interface Timing Characteristics................................................7
Absolute Maximum Ratings............................................................8
ESD Caution..................................................................................8
Pin Configuration and Function Description..............................9 2C Interface Timing Diagram....................................................9 2C Interface General Description................................................10 2C Interface Detail Description...................................................11
RDAC/EEMEM Write...............................................................11 2C Compatible 2-Wire Serial Bus................................................15
Typical Performance Characteristics...........................................16
Operational Overview....................................................................20
Linear Increment and Decrement Commands......................20
±6 dB Adjustments (Doubling/Halving WIPER Setting).....20
Digital Input/Output Configuration........................................21
Multiple Devices on One Bus...................................................21
Terminal Voltage Operation Range.........................................21
Power-Up and Power-Down Sequences..................................21
Layout and Power Supply Biasing............................................22
Digital Potentiometer Operation.............................................22
Programmable Rheostat Operation.........................................22
Programmable Potentiometer Operation...............................23
Applications.....................................................................................24
LCD Panel Vcom Adjustment.....................................................24
Current-Sensing Amplifier.......................................................24
Adjustable High Power LED Driver........................................24
Outline Dimensions.......................................................................25
Ordering Guide..........................................................................25
REVISION HISTORY
6/04—Revision 0: Initial Version
ELECTRICAL CHARACTERISTICS
1 kΩ Version. VDD = 3 V ± 10% or 5 V ± 10%; VSS = 0 V or VDD/VSS = ± 2.5 V ± 10%; VA = +VDD, VB = 0 V, –40°C < TA < +85°C, unless
otherwise noted.
Table 1.
Typical represents the average reading at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ
version at VDD = 2.7 V, IW = VDD/R for both VDD = 3 V or VDD = 5 V. INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL
specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.
5 Guaranteed by design and not subject to production test. cmd 0 NOP should be activated after cmd 1 to minimize IDD_READ current consumption.
7 PDISS is calculated from IDD × VDD = 5 V. All dynamic characteristics use VDD = 5 V.
10 kΩ, 50 kΩ, 100 kΩ Versions. VDD = +3 V ± 10% or + 5 V ± 10%. VSS = 0 V or VDD/VSS = ± 2.5 V ± 10%. VA = +VDD, VB = 0 V,
–40°C < TA < +85°C, unless otherwise noted.
Table 2.
Typical represents the average reading at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ
version at VDD = 2.7 V, IW = VDD/R for both VDD = 3 V or VDD = 5 V. INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL
specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
4 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other. Guaranteed by design and not subject to production test.
6 cmd 0 NOP should be activated after cmd 1 to minimize IDD_READ current consumption. PDISS is calculated from IDD × VDD = 5 V.
8 All dynamic characteristics use VDD = 5 V.
INTERFACE TIMING CHARACTERISTICS
Guaranteed by design, not subject to production test. See Figure 3 for location of measured values. All input control voltages are
specified with tR = tF = 2.5 ns (10% to 90% of 3 V), and timed from a voltage level of 1.5 V. Switching characteristics are measured
using both VDD = 3 V and 5 V.
Table 3. Interface Timing and EEMEM Reliability Characteristics (All Parts). During power-up, all outputs preset to midscale before restoring to the final EEMEM contents. RDAC0 has the shortest, whereas RDAC3 has the longest EEMEM data
restoring time. Retention lifetime equivalent at junction temperature TJ = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates
with junction temperature. When the part is not in operation, the SDA and SCL pins should be pulled to high. When these pins are pulled to low, the I2C interface at these pins conducts current of
about 0.8 mA at VDD = 5.5 V and 0.2 mA at VDD = 2.7 V.
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted .
Table 4. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1 Maximum terminal current is bounded by the maximum applied voltage
across any two of the A, B, and W terminals at a given resistance, the
maximum current handling of the switches, and the maximum power
dissipation of the package. VDD = 5 V.
2 Package power dissipation = (TJMAX − TA)/θJA.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTION
AD0
SDA
VDD
AD1
VSS
SCL
DGNDAD5251/
AD5252
TOP VIEW
(Not to Scale)
Figure 2. AD5251/AD5252 in TSSOP-14
Table 5. Pin Function Descriptions For quad-channel device software compatibility, the dual potentiometers in the parts are designated as RDAC1 and RDAC3.
2C INTERFACE TIMING DIAGRAM
SCL
SDAP03823-0-003
t52C INTERFACE GENERAL DESCRIPTION 0 WRITE
DATA TRANSFERRED
(N BYTES + ACKNOWLEDGE)FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
S = START CONDITION
P = STOP CONDITION
A = ACKNOWLEDGE (SDA LOW)
A = NOT ACKNOWLEDGE (SDA HIGH)
R/W = READ ENABLE AT HIGH AND WRITE ENABLE AT LOW
Figure 4. I2C—Master Writing Data to Slave
1 READ
DATA TRANSFERRED
(N BYTES + ACKNOWLEDGE)Figure 5. I2C—Master Reading Data from Slave
READ OR WRITE(N BYTES +
ACKNOWLEDGE)03823-0-006
REPEATED STARTREAD
OR WRITE
DIRECTION OF TRANSFER MAY
CHANGE AT THIS POINT
(N BYTES +
ACKNOWLEDGE)Figure 6. I2C—Combined Write/Read
2C INTERFACE DETAIL DESCRIPTION 0 WRITE(1 BYTE +
ACKNOWLEDGE)
SLAVE ADDRESSINSTRUCTIONS
AND ADDRESS
0 REG
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
S = START CONDITIONP = STOP CONDITION
A = ACKNOWLEDGE (SDA LOW)
A = NOT ACKNOWLEDGE (SDA HIGH)R/W = READ ENABLE AT HIGH AND WRITE ENABLE AT LOW
CMD/REG = COMMAND ENABLE BIT, LOGIC HIGH/REGISTER ACCESS BIT, LOGIC LOW
EE/RDAC = EEMEM REGISTER, LOGIC HIGH/RDAC REGISTER, LOGIC LOWA4, A3, A2, A1, A0 = RDAC/EEMEM REGISTER ADDRESSES
Figure 7. Single Write Mode
0 WRITE03823-0-008
(N BYTES +
ACKNOWLEDGE)
RDAC SLAVE ADDRESSRDAC INSTRUCTIONS
AND ADDRESS
0 REGFigure 8. Consecutive Write Mode
Table 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/W = 0, CMD/REG = 0, EE/RDAC = 0)
RDAC/EEMEM WRITE Setting the wiper position requires an RDAC write operation.
The single write operation is shown in Figure 7, and the
consecutive write operation is shown in Figure 8. In the
consecutive write operation, if the RDAC is selected and the
address starts at 00001, the first data byte goes to RDAC1 and
the second data byte goes to RDAC3. The RDAC address is
shown in Table 6.
While the RDAC wiper setting is controlled by a specific RDAC
register, each RDAC register corresponds to a specific EEMEM
location, which provides nonvolatile wiper storage functionality.
There are 12 nonvolatile memory locations: EEMEM4 to
EEMEM15. Users can store a total of 12 bytes of information,
such as memory data for other components, look-up tables, or
system identification information.
In a write operation to the EEMEM registers, the device disables
the I2C interface during the internal write cycle. Acknowledge
polling is required to determine the completion of the write
cycle. See EEMEM Write-Acknowledge Polling.
Table 7. Addresses for Writing (Storing) RDAC Settings and
User-Defined Data to EEMEM Registers (R/W = 0,
CMD/REG = 0, EE/RDAC = 1) User can store any of the 64 RDAC settings for AD5251 or any of the 256
RDAC settings for AD5252.
RDAC/EEMEM Read The AD5251/AD5252 provide two different RDAC or EEMEM
read operations. For example, Figure 9 shows the method of
reading the RDAC0 to RDAC3 contents without specifying the
address, assuming Address RDAC0 was already selected from
the previous operation. If RDAC_N, other than Address 0, is
selected previously, readback starts with Address N, followed by
N + 1, and so on.
Figure 10 illustrates a random RDAC or EEMEM read
operation. This operation lets users specify which RDAC or
EEMEM register is read by first issuing a dummy write
command to change the RDAC address pointer, and then
proceeding with the RDAC read operation at the new address
location.
Table 8. Addresses for Reading (Restoring) RDAC Settings
and User Data from EEMEM (R/W = 1, CMD/REG = 0,
EE/RDAC = 1)
1 READ03823-0-009
RDAC SLAVE ADDRESS(N BYTES + ACKNOWLEDGE)Figure 9. RDAC Current Read (Restricted to Previously Selected Address Stored in the Register).
0 WRITE03823-0-010
REPEATED START1 READ
(N BYTES + ACKNOWLEDGE)Figure 10. RDAC or EEMEM Random Read
RDAC/EEMEM Quick Commands The AD5251/AD5252 feature 12 quick commands that facilitate
easy manipulation of RDAC wiper settings and provide RDAC-
to-EEMEM storing and restoring functions. The command
format is shown in Figure 11 and the command descriptions are
shown in Table 9.
0 WRITE03823-0-011
1 CMD
RDAC SLAVE ADDRESS
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
S = START CONDITION
P = STOP CONDITION
A = ACKNOWLEDGE (SDA LOW)
A = NOT ACKNOWLEDGE (SDA HIGH)
AD1, AD0 = I2C DEVICE ADDRESS BITS. MUST MATCH WITH THE LOGIC STATES AT PINS AD1, AD0
R/W = READ ENABLE BIT, LOGIC HIGH/WRITE ENABLE BIT, LOGIC LOW
CMD/REG = COMMAND ENABLE BIT, LOGIC HIGH/REGISTER ACCESS BIT, LOGIC LOW
C3, C2, C1, C0 = COMMAND BITS
A2, A1, A0 = RDAC/EEMEM REGISTER ADDRESSESFigure 11. RDAC Quick Command Write (Dummy Write)
Table 9. RDAC-to-EEMEM Interface and RDAC Operation Quick Command Bits (CMD/REG = 1, A2 = 0) This command leaves the device in the EEMEM read power state, which consumes power. Users should issue the NOP command to return the device to the idle state.
Table 10. Address Table for Reading Tolerance (CMD/REG = 0, EE/RDAC = 1, A4 = 1)
03823-0-012
D7D6D5D4D3D2D1D0
SIGN
SIGN7 BITS FOR INTEGER NUMBER252423222120D7D6D5D4D3D2D1D0
8 BITS FOR DECIMAL NUMBER
2–82–12–22–32–42–52–62–7Figure 12. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions. (Unit is percent. Only data bytes are shown.)
RAB Tolerance Stored in Read-Only Memory The AD5251/AD5252 feature patented RAB tolerances storage in
the nonvolatile memory. The tolerance of each channel is stored
in the memory during the factory production and can be read
by users at any time. The knowledge of stored tolerance, which
is the average of RAB over all codes (see Figure 28), allows users
to predict RAB accurately. This feature is valuable for precision,
rheostat mode, and open-loop applications where knowledge of
absolute resistance is critical.
The stored tolerances reside in the read-only memory, and are
expressed as a percentage. The tolerance is stored in two
memory locations (see Table 10). The data format of the
tolerance is in sign magnitude binary form. An example is
shown in Figure 11. In the first memory location, the MSB is
designated for the sign (0 = + and 1= –) and the 7 LSBs are
designated for the integer portion of the tolerance. In the
second memory location, all eight data bits are designated for
the decimal portion of tolerance. As shown in Table 10 and
Figure 12 for example, if the rated RAB = 10 kΩ and the data
readback from Address 11000 shows 0001 1100 and Address
11001 shows 0000 1111, then RDAC0 tolerance can be
calculated as
MSB: 0 = +
Next 7 MSB: 001 1100 = 28
8 LSB: 0000 1111 = 15 × 2–8 = 0.06
Tolerance = +28.06% and therefore
RAB_ACTUAL = 12.806 kΩ
EEMEM Write-Acknowledge Polling After each write operation to the EEMEM registers, an internal
write cycle begins. The I2C interface of the device is disabled. To
determine if the internal write cycle is complete and the I2C
interface is enabled, interface polling can be executed. I2C
interface polling can be conducted by sending a start condition
followed by the slave address + the write bit. If the I2C interface
responds with an ACK, the write cycle is complete and the
interface is ready to proceed with further operations. Other-
wise, I2C interface polling can be repeated until it succeeds.
Commands 2 and 7 also require acknowledge polling.
EEMEM Write Protection Setting the WP pin to a logic LOW after EEMEM programming
protects the memory and RDAC registers from future write
operations. In this mode, the EEMEM and RDAC read
operations operate as normal. When write protection is
enabled, Command 1 (Restore from EEMEM to RDAC) and
Command 7 (Reset) function normally to allow RDAC settings
to be refreshed from the EEMEM to the RDAC registers.
