AD524AD-AD524AR-16-AD524BD-AD524BE-AD524CD-AD524SD-AD524SD/883B Fast Delivery |IC PHOENIX CO.,LIMITED

AD524BD ,Precision Instrumentation Amplifierapplications.90 dB at unity gain (120 dB at G = 1000) and maximum non-4. The AD524 is input protect ..
AD524BD ,Precision Instrumentation Amplifierapplications.90 dB at unity gain (120 dB at G = 1000) and maximum non-4. The AD524 is input protect ..
AD524BE ,Precision Instrumentation Amplifierspecifications, the AD524 also has a 25 kHz gain bandwidthproduct (G = 1000). To make it suitable f ..
AD524CD ,Precision Instrumentation Amplifierspecifications, the AD524 also has a 25 kHz gain bandwidthproduct (G = 1000). To make it suitable f ..
AD524SD ,Precision Instrumentation Amplifierapplications.designed for data acquisition
AD524SD/883B ,Precision Instrumentation AmplifierFEATURESLow Noise: 0.3 mV p-p 0.1 Hz to 10 HzLow Nonlinearity: 0.003% (G = 1)PROTECTION–INPUTHigh C ..
AD9054ABST-200 ,8-Bit, 200 MSPS A/D Converterapplications. Fabricated with an advanced BiCMOS process, the AD9054A isprovided in a space-saving ..
AD9054ABST-200 ,8-Bit, 200 MSPS A/D ConverterGENERAL DESCRIPTION The AD9054A’s encode input interfaces directly to TTL, CMOSThe AD9054A is an 8- ..
AD9054BST-135 ,8-Bit, 200 MSPS A/D ConverterCHARACTERISTICS DD STest AD9054BST-200 AD9054BST-135Parameter Temp Level Min Typ Max Min T ..
AD9054BST-200 ,8-Bit, 200 MSPS A/D ConverterGENERAL DESCRIPTIONchannel digital outputs. The dual (demultiplexed) mode inter-The AD9054 is an 8 ..
AD9057BRS-40 ,8-Bit 40 MSPS/50 MSPS/80 MSPS ConverterSPECIFICATIONSD DDTest AD9057BRS-40 AD9057BRS-60 AD9057BRS-80Parameter Temp Level Min Typ Max ..
AD9057BRS-60 ,8-Bit 40 MSPS/60 MSPS/80 MSPS A/D ConverterSPECIFICATIONSD DDTest AD9057BRS-40 AD9057BRS-60 AD9057BRS-80Parameter Temp Level Min Typ Max ..

AD524AD-AD524AR-16-AD524BD-AD524BE-AD524CD-AD524SD-AD524SD/883B
Precision Instrumentation Amplifier
REV.EPrecision
Instrumentation Amplifier
FEATURES
Low Noise: 0.3 mV p-p 0.1 Hz to 10 Hz
Low Nonlinearity: 0.003% (G = 1)
High CMRR: 120 dB (G = 1000)
Low Offset Voltage: 50 mV
Low Offset Voltage Drift: 0.5 mV/8C
Gain Bandwidth Product: 25 MHz
Pin Programmable Gains of 1, 10, 100, 1000
Input Protection, Power On–Power Off
No External Components Required
Internally Compensated
MIL-STD-883B and Chips Available
16-Lead Ceramic DIP and SOIC Packages and
20-Terminal Leadless Chip Carriers Available
Available in Tape and Reel in Accordance
with EIA-481A Standard
Standard Military Drawing Also Available
PRODUCT DESCRIPTION
The AD524 is a precision monolithic instrumentation amplifier
designed for data acquisition applications requiring high accu-
racy under worst-case operating conditions. An outstanding
combination of high linearity, high common mode rejection, low
offset voltage drift and low noise makes the AD524 suitable for
use in many data acquisition systems.
The AD524 has an output offset voltage drift of less than 25 mV/°C,
input offset voltage drift of less than 0.5 mV/°C, CMR abovedB at unity gain (120 dB at G = 1000) and maximum non-
linearity of 0.003% at G = 1. In addition to the outstanding dc
specifications, the AD524 also has a 25 kHz gain bandwidth
product (G = 1000). To make it suitable for high speed data
acquisition systems the AD524 has an output slew rate of 5 V/ms
and settles in 15 ms to 0.01% for gains of 1 to 100.
As a complete amplifier the AD524 does not require any exter-
nal components for fixed gains of 1, 10, 100 and 1000. For
other gain settings between 1 and 1000 only a single resistor is
required. The AD524 input is fully protected for both power-on
and power-off fault conditions.
The AD524 IC instrumentation amplifier is available in four
different versions of accuracy and operating temperature range.
The economical “A” grade, the low drift “B” grade and lower
drift, higher linearity “C” grade are specified from –25°C to
+85°C. The “S” grade guarantees performance to specification
over the extended temperature range –55°C to +125°C. Devices
are available in 16-lead ceramic DIP and SOIC packages and a
20-terminal leadless chip carrier.
PRODUCT HIGHLIGHTS
1. The AD524 has guaranteed low offset voltage, offset voltage
drift and low noise for precision high gain applications.
2. The AD524 is functionally complete with pin programmable
gains of 1, 10, 100 and 1000, and single resistor program-
mable for any gain.
3. Input and output offset nulling terminals are provided for
very high precision applications and to minimize offset volt-
age changes in gain ranging applications.
4. The AD524 is input protected for both power-on and power-
off fault conditions.
5. The AD524 offers superior dynamic performance with a gain
bandwidth product of 25 MHz, full power response of 75 kHz
and a settling time of 15 ms to 0.01% of a 20 V step (G = 100).
FUNCTIONAL BLOCK DIAGRAM
INPUT CURRENT
AD524–SPECIFICATIONS
(@ VS = 615 V, RL = 2 kV and TA = +258C unless otherwise noted)
REFERENCE INPUT
TEMPERATURE RANGE
POWER SUPPLY
NOTESDoes not include effects of external resistor RG.VOL is the maximum differential input voltage at G = 1 for specified nonlinearity.
VDL at the maximum = 10 V/G.
VD = Actual differential input voltage.
Example: G = 10, VD = 0.50.
VCM = 12 V – (10/2 · 0.50 V) = 9.5 V.
Specification subject to change without notice.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to
calculate outgoing quality levels.
AD524
AD524
METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
OUTPUT
NULLG = 101312111054
G = 100G = 1000SENSE
OUTPUT
+VS
REFERENCEINPUT
NULL
RG2
+INPUT
–INPUT
RG1
OUTPUT
NULL
NULL
–VS
PAD NUMBERS CORRESPOND TO PIN NUMBERS FOR THE
D-16 AND R-16 16-PIN CERAMIC PACKAGES.
NOTESStresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the operational section of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2Max input voltage specification refers to maximum voltage to which either input
terminal may be raised with or without device power applied. For example, with –18
volt supplies max VIN is –18 volts, with zero supply voltage max VIN is –36 volts.
ABSOLUTE MAXIMUM RATINGSl
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . .450 mW
Input Voltage2
(Either Input Simultaneously) |VIN| + |VS| . . . . . . . .<36 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . .Indefinite
Storage Temperature Range
(R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
(D, E) . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
AD524A/B/C . . . . . . . . . . . . . . . . . . . . . . . .–25°C to +85°C
AD524S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature (Soldering 60 secs) . . . . . . . . . . . . +300°C
CONNECTION DIAGRAMS
Ceramic (D) and
SOIC (R) Packages
–VS+VS
OUTPUT
OFFSET NULL
INPUT
OFFSET NULL
– INPUT
+ INPUT
RG2
INPUT NULL
INPUT NULL
REFERENCE
–VS
+VS
RG1
OUTPUT NULL
OUTPUT NULL
G = 10
G = 100
G = 1000
SENSE
OUTPUTSHORT TO
RG2 FOR
DESIRED
GAIN
Leadless Chip Carrier
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ORDERING GUIDERefer to official DESC drawing for tested specifications.
Figure 3. Output Voltage Swing vs.
Load Resistance
TEMPERATURE – 8C
INPUT BIAS CURRENT – nA
–10
Figure 6.Input Bias Current vs.
Temperature
FREQUENCY – Hz
GAIN – V/V1010M1001k10k100k1M
100
Figure 9.Gain vs. Frequency
SUPPLY VOLTAGE – 6V
OUTPUT VOLTAGE SWING – 05201015
Figure 2.Output Voltage Swing vs.
Supply Voltage
SUPPLY VOLTAGE – 6V
INPUT BIAS CURRENT – 05201015
Figure 5.Input Bias Current vs.
Supply Voltage
WARM-UP TIME – Minutes
FROM FINAL VALUE – 1.08.02.03.04.05.06.07.0
Figure 8.Offset Voltage, RTI, Turn
On Drift
SUPPLY VOLTAGE – 6V
INPUT VOLTAGE – 05201015
Figure 1.Input Voltage Range vs.
Supply Voltage, G = 1
SUPPLY VOLTAGE – 6V
QUIESCENT CURRENT – mA
2.0
Figure 4.Quiescent Current vs.
Supply Voltage
INPUT VOLTAGE – 6V
INPUT BIAS CURRENT – 05201015
Figure 7.Input Bias Current vs. Input
Voltage
AD524
FREQUENCY – Hz
CMRR – dB1010M1001k10k100k1M
Figure 10.CMRR vs. Frequency RTI,
Zero to 1k Source Imbalance
FREQUENCY – Hz100k1001k10k
POWER SUPPLY REJECTION – dB
Figure 13.Positive PSRR vs.
Frequency
FREQUENCY – Hz
CURRENT NOISE SPECTRAL DENSITY – fA/100k
10k110k101001k
100
Figure 16.Input Current Noise vs.
Frequency
FREQUENCY – Hz
FULL POWER RESPONSE – V
p-p1k10k1M100k
Figure 11.Large Signal Frequency
Response
FREQUENCY – Hz100k1001k10k
POWER SUPPLY REJECTION – dB
Figure 14.Negative PSRR vs.
Frequency
0.1 – 10Hz
VERTICAL SCALE; 1 DIVISION = 5mV
Figure 17.Low Frequency Noise␣–
G = 1 (System Gain = 1000)
SLEW RATE –V/
GAIN – V/V
2.0
Figure 12.Slew Rate vs. Gain
Figure 15.RTI Noise Spectral
Density vs. Gain
0.1 – 10Hz
VERTICAL SCALE; 1 DIVISION = 0.1mV
Figure 18.Low Frequency Noise –
G = 1000 (System Gain = 100,000)
Figure 21.Settling Time Gain = 10
Figure 24.Large Signal Pulse
Response and Settling Time
G = 100
Figure 20.Large Signal Pulse
Response and Settling Time – G =1
SETTLING TIME – ms
–12 TO +12
+4 TO –4
+8 TO –8
+12 TO –12
–8 TO +8
–4 TO +4
OUTPUT
STEP – V
Figure 23.Settling Time Gain = 100
Figure 26.Large Signal Pulse Re-
sponse and Settling Time G = 1000
SETTLING TIME – ms
–12 TO +12
+4 TO –4
+8 TO –8
+12 TO –12
–8 TO +8
–4 TO +4
OUTPUT
STEP – V
Figure 19.Settling Time Gain = 1
Figure 22.Large Signal Pulse
Response and Settling Time
G = 10
SETTLING TIME – ms
–12 TO +12
+4 TO –4
+8 TO –8
+12 TO –12
–8 TO +8
–4 TO +4
OUTPUT
STEP – V103050
Figure 25.Settling Time Gain = 1000
AD524
Theory of Operation
The AD524 is a monolithic instrumentation amplifier based on
the classic 3 op amp circuit. The advantage of monolithic con-
struction is the closely matched components that enhance the
performance of the input preamp. The preamp section develops
the programmed gain by the use of feedback concepts. The
programmed gain is developed by varying the value of RG (smaller
values increase the gain) while the feedback forces the collector
currents Q1, Q2, Q3 and Q4 to be constant, which impresses
the input voltage across RG.
–VS
INPUT
20V p-p
10kV
0.01%
1kV
10T
10kV
0.1%
Figure 27.Settling Time Test Circuit
–IN
+VS
+IN
REFERENCE
SENSE
50mA
–VS
Figure 28Simplified Circuit of Amplifier; Gain Is Defined as
((R56 + R57)/(RG)) + 1. For a Gain of 1, RG Is an Open Circuit
As RG is reduced to increase the programmed gain, the trans-
conductance of the input preamp increases to the transconduct-
ance of the input transistors. This has three important advantages.
First, this approach allows the circuit to achieve a very high
open loop gain of 3 · 108 at a programmed gain of 1000, thus
reducing gain-related errors to a negligible 30 ppm. Second, the
gain bandwidth product, which is determined by C3 or C4 and
the input transconductance, reaches 25 MHz. Third, the input
voltage noise reduces to a value determined by the collector
current of the input transistors for an RTI noise of 7 nV/�Hz at
G = 1000.
INPUT PROTECTION
As interface amplifiers for data acquisition systems, instrumen-
tation amplifiers are often subjected to input overloads, i.e.,
voltage levels in excess of the full scale for the selected gain
range. At low gains, 10 or less, the gain resistor acts as a current
limiting element in series with the inputs. At high gains the
lower value of RG will not adequately protect the inputs from
excessive currents. Standard practice would be to place series
limiting resistors in each input, but to limit input current to
below 5 mA with a full differential overload (36 V) would re-
quire over 7k of resistance which would add 10 nV�Hz of noise.
To provide both input protection and low noise a special series
protect FET was used.
A unique FET design was used to provide a bidirectional cur-
rent limit, thereby, protecting against both positive and negative
overloads. Under nonoverload conditions, three channels CH2,
CH3, CH4, act as a resistance (»1 kW) in series with the input as
before. During an overload in the positive direction, a fourth
channel, CH1, acts as a small resistance (»3 kW) in series with
the gate, which draws only the leakage current, and the FET
limits IDSS. When the FET enhances under a negative overload,
the gate current must go through the small FET formed by CH1
and when this FET goes into saturation, the gate current is
limited and the main FET will go into controlled enhancement.
The bidirectional limiting holds the maximum input current to
3 mA over the 36 V range.
INPUT OFFSET AND OUTPUT OFFSET
Voltage offset specifications are often considered a figure of
merit for instrumentation amplifiers. While initial offset may be
adjusted to zero, shifts in offset voltage due to temperature
variations will cause errors. Intelligent systems can often correct
for this factor with an autozero cycle, but there are many small-
signal high-gain applications that don’t have this capability.
16.2kV1.82kV

Partno	Mfg	Dc	Qty	Available	Descript
AD524AD		N/a	18	avai	Precision Instrumentation Amplifier
AD524AR-16 \|AD524AR16	AD	N/a	20	avai	Precision Instrumentation Amplifier
AD524BD	AD	N/a	800	avai	Precision Instrumentation Amplifier
AD524BD	ADI	N/a	16	avai	Precision Instrumentation Amplifier
AD524BE		N/a	64	avai	Precision Instrumentation Amplifier
AD524CD	AD	N/a	200	avai	Precision Instrumentation Amplifier
AD524SD	ADI	N/a	9	avai	Precision Instrumentation Amplifier
AD524SD/883B \|AD524SD883B	AD ?	N/a	7	avai	Precision Instrumentation Amplifier