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AD5247-AD5247BKS100-RL7-AD5247BKS5RL7-AD5247BKS5-RL7
128 Position I2C Compatible Digital Potentiometer in SC70 Package
128-Position I2C Compatible
Digital Potentiometer
FEATURES
128-position
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Ultracompact SC70-6 (2 mm × 2.1 mm) package 2C® compatible interface
Full read/write of wiper register
Power-on preset to midscale
Single supply 2.7 V to 5.5 V
Low temperature coefficient 45 ppm/°C
Low power, IDD = 3 µA typical
Wide operating temperature –40°C to +125°C
Evaluation board available
APPLICATIONS
Mechanical potentiometer replacement in new designs
Rev.0
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
LCD brightness and contrast adjustment
Automotive electronics adjustment
Gain control and offset adjustment
GENERAL OVERVIEW The AD5247 provides a compact 2 mm × 2.1 mm packaged
solution for 128-position adjustment applications. This device
performs the same electronic adjustment function as a
mechanical potentiometer or a variable resistor. Available in
four different end-to-end resistance values (5 kΩ, 10 kΩ, 50 kΩ,
100 kΩ), these low temperature coefficient devices are ideal for
high accuracy and stability variable resistance adjustments.
The wiper settings are controllable through the I2C compatible
digital interface, which can also be used to read back the present
wiper register control word. The resistance between the wiper
and either end point of the fixed resistor varies linearly with
respect to the digital code transferred into the RDAC1 latch.
Operating from a 2.7 V to 5.5 V power supply and consuming
3 µA allows for usage in portable battery-operated applications.
FUNCTIONAL BLOCK DIAGRAM
SCL
SDA
GND
VDD
03876-0-001Figure 1.
1 Note: The terms digital potentiometer, VR, and RDAC are used
interchangeably in this document.
TABLE OF CONTENTS
Electrical Characteristics—5 kΩ Version......................................3
Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions.......4
Timing Characteristics
5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions........................................5
Absolute Maximum Ratings............................................................6
Typical Performance Characteristics.............................................7
Test Circuits.....................................................................................11 2C Interface.....................................................................................12
Operation.........................................................................................13
Programming the Variable Resistor.........................................13
Programming the Potentiometer Divider...............................14 2C Compatible 2-Wire Serial Bus............................................14
Level Shifting for Bidirectional Interface................................15
ESD Protection...........................................................................15
Terminal Voltage Operating Range..........................................15
Maximum Operating Current..................................................15
Power-Up Sequence...................................................................15
Layout and Power Supply Bypassing.......................................16
Constant Bias to Retain Resistance Setting.............................16
Evaluation Board........................................................................16
Pin Configuration and Function Descriptions...........................17
Outline Dimensions.......................................................................18
Ordering Guide..........................................................................18
REVISION HISTORY
Revision 0: Initial Version
ELECTRICAL CHARACTERISTICS—5 kΩ VERSION
Table 1. VDD = 5 V ±10% or 3 V ± 10%; VA = +VDD; –40°C < TA < +125°C; unless otherwise noted
1 Typical specifications represent average readings at 25°C and VDD = 5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. VA = VDD, Wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor terminals A and W have no limitations on polarity with respect to each other. Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. All dynamic characteristics use VDD = 5 V.
ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS
Table 2. VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; –40°C < TA < +125°C; unless otherwise noted
Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VA = VDD, Wiper (VW) = no connect. INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. Resistor terminals A and W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test. PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS
Table 3. VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; –40°C < TA < +125°C; unless otherwise noted
1 Typical specifications represent average readings at 25°C and VDD = 5 V. Guaranteed by design and not subject to production test.
3 See timing diagrams (, Figu, ) for locations of measured values. Figure 31re 32Figure 33
ABSOLUTE MAXIMUM RATINGS
Table 4. TA = 25°C, unless otherwise noted1
1 Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
2 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
3 Package power dissipation = (TJMAX – TA)/θJA.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
TYPICAL PERFORMANCE CHARACTERISTICS
CODE (Decimal)
RHE
TAT MODE
INL (LS–1.0
RHE
TAT MODE
INL (LS
Figure 2. R-INL vs. Code vs. Supply Voltages
CODE (Decimal)
RHE
TAT MODE
DNL (LS
03876-0-035
Figure 3. R-DNL vs. Code vs. Supply Voltages
CODE (Decimal)
NTIOME
R MODE
INL (LS
03876-0-036
CODE (Decimal)
NTIOME
R MODE
DNL (LS–0.25
03876-0-037
Figure 5. DNL vs. Code vs. Temperature
CODE (Decimal)–0.25
NTIOME
R MODE
INL (LS
03876-0-038
Figure 6. INL vs. Code vs. Supply Voltages
CODE (Decimal)–0.25
NTIOME
R MODE
DNL (LS
03876-0-039
CODE (Decimal)
RHEOSTAT MODE INL (LSB)
03876-0-040
Figure 8. R-INL vs. Code vs. Temperature
CODE (Decimal)
RHE
TAT MODE
DNL (LS
03876-0-041
Figure 9. R-DNL vs. Code vs. Temperature
TEMPERATURE (°C)
RHEOSTAT MODE INL (LSB)
FSE, FU
LL-
E ER110125
03876-0-042
Figure 10. Full-Scale Error vs. Temperature
TEMPERATURE (°C)
, ZE
RO-S
CALE
RROR (LS
03876-0-043
Figure 11. Zero-Scale Error vs. Temperature
TEMPERATURE (°C)
IDD,
CURRE
NT (
100203550658095110125
Figure 12. Supply Current vs. Temperature
CODE (Decimal)
RHE
TAT MODE
TEMPCO (ppm/
°C)–500
03876-0-045
Figure 13. Rheostat Mode Tempco ∆RWB/∆T vs. Code
CODE (Decimal)
POTENTIOMETER (ppm/
°C)
–1032488096112128
Figure 14. Potentiometer Mode Tempco ∆VWB/∆T vs. Code
GAIN (
10k
100k1M10M–60
FREQUENCY (Hz)
Figure 15. Gain vs. Frequency vs. Code, RAB = 5 kΩ
10k
100k1M10M–60
GAIN (
FREQUENCY (Hz)
Figure 16. Gain vs. Frequency vs. Code, RAB = 10 kΩ
10k
100k1M10M–60
GAIN (
FREQUENCY (Hz)
Figure 17. Gain vs. Frequency vs. Code, RAB = 50 kΩ
10k
100k1M10M–60
GAIN (
FREQUENCY (Hz)
Figure 18. Gain vs. Frequency vs. Code, RAB = 100 kΩ
10k
100k1M10M–60
GAIN (
FREQUENCY (Hz)
Figure 19. –3 dB Bandwidth @ Code = 0x80
FREQUENCY (Hz)
10k100k1M0
03876-0-052
Figure 20. IDD vs. Frequency
WIP
RE
ANCE
CODE (Decimal)
03876-0-056
Figure 21. Wiper Resistance vs. Code vs. VDD
1µs/DIV
Figure 22. Digital Feedthrough
200ns/DIV
Figure 23. Midscale Glitch, Code 0x40 to 0x3F
4µs/DIV
Figure 24. Large Signal Settling Time
