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AD5246BKS5-RL7-AD5246BKSZ100-R2
128 Position I2C Compatible Programmable Resistor in SC70 Package
128-Position I2C Compatible
Digital Resistor
FEATURES
128-position
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Ultracompact SC70-6 (2 mm × 2.1 mm) package 2C® compatible interface
Full read/write of wiper register
Power-on preset to midscale
Single supply 2.7 V to 5.5 V
Low temperature coefficient 45 ppm/°C
Low power, IDD = 3 µA typical
Wide operating temperature –40°C to +125°C
Evaluation board available
APPLICATIONS
Mechanical potentiometer replacement in new designs
Rev.0
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
GENERAL OVERVIEW The AD5246 provides a compact 2 mm × 2.1 mm packaged
solution for 128-position adjustment applications. This device
performs the same electronic adjustment function as a variable
resistor. Available in four different end-to-end resistance values
(5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ), these low temperature coefficient
devices are ideal for high accuracy and stability variable
resistance adjustments.
The wiper settings are controllable through the I2C compatible
digital interface, which can also be used to read back the present
wiper register control word. The resistance between the wiper
and either end point of the fixed resistor varies linearly with
respect to the digital code transferred into the RDAC1 latch.
Operating from a 2.7 V to 5.5 V power supply and consuming
3 µA allows for usage in portable battery-operated applications.
FUNCTIONAL BLOCK DIAGRAM
SCL
GND
VDD
03875-0-001Figure 1.
1 Note: The terms digital potentiometer, VR, and RDAC are used
interchangeably in this document.
TABLE OF CONTENTS
Electrical Characteristics—5 kΩ Version......................................3
Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions.......4
Timing Characteristics—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions5
Absolute Maximum Ratings............................................................6
Typical Performance Characteristics.............................................7
Test Circuits.....................................................................................10 2C Interface.....................................................................................11
Operation.........................................................................................12
Programming the Variable Resistor.........................................12 2C Compatible 2-Wire Serial Bus............................................13
Level Shifting for Bidirectional Interface................................13
ESD Protection...........................................................................13
Terminal Voltage Operating Range..........................................14
Maximum Operating Current..................................................14
Power-Up Sequence...................................................................14
Layout and Power Supply Bypassing.......................................14
Constant Bias to Retain Resistance Setting.............................15
Evaluation Board........................................................................15
Pin Configuration and Function Descriptions...........................16
Outline Dimensions.......................................................................17
Ordering Guide..........................................................................17
REVISION HISTORY
Revision 0: Initial Version
ELECTRICAL CHARACTERISTICS—5 kΩ VERSION
Table 1. VDD = 5 V ±10% or 3 V ± 10%; VA = +VDD; –40°C < TA < +125°C; unless otherwise noted
1 Typical specifications represent average readings at 25°C and VDD = 5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. Code = 0x7F.
4 Resistor terminals A and W have no limitations on polarity with respect to each other. Guaranteed by design and not subject to production test.
6 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. All dynamic characteristics use VDD = 5 V.
ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS
Table 2. VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; –40°C < TA < +125°C; unless otherwise noted
1 Typical specifications represent average readings at +25°C and VDD = 5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. Code = 0x7F.
4 Resistor terminals A and W have no limitations on polarity with respect to each other. Guaranteed by design and not subject to production test.
6 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. All dynamic characteristics use VDD = 5 V.
TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS
Table 3. VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; –40°C < TA < +125°C; unless otherwise noted
1 Typical specifications represent average readings at 25°C and VDD = 5 V. Guaranteed by design and not subject to production test.
3 See timing diagrams (, Figu, ) for locations of measured values. Figure 25re 26Figure 27
ABSOLUTE MAXIMUM RATINGS
Table 4. TA = 25°C, unless otherwise noted1
1 Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
2 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
3 Package power dissipation = (TJMAX – TA)/θJA.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
TYPICAL PERFORMANCE CHARACTERISTICS
CODE (Decimal)
RHE
TAT MODE
INL (LS–1.0
RHE
TAT MODE
INL (LS
Figure 2. R-INL vs. Code vs. Supply Voltages
CODE (Decimal)
RHE
TAT MODE
DNL (LS–0.5
03875-0-021
Figure 3. R-DNL vs. Code vs. Supply Voltages
CODE (Decimal)
RHEOSTAT MODE INL (LSB)–1.0
03875-0-022
Figure 4. R-INL vs. Code vs. Temperature
CODE (Decimal)
RHE
TAT MODE
DNL (LS–0.5
03875-0-023
Figure 5. R-DNL vs. Code vs. Temperature
TEMPERATURE (°C)
RHEOSTAT MODE INL (LSB)
FSE, FU
LL-
E ER110125
03875-0-024
Figure 6. Full-Scale Error vs. Temperature
TEMPERATURE (°C)
, ZE
RO-S
CALE
RROR (LS
03875-0-025
Figure 7. Zero-Scale Error vs. Temperature
TEMPERATURE (°C)
IDD,
CURRE
NT (
100203550658095110125
Figure 8. Supply Current vs. Temperature
CODE (Decimal)
RHE
TAT MODE
TEMPCO (ppm/
°C)–500
03875-0-027
Figure 9. Rheostat Mode Tempco ∆RWB/∆T vs. Code
GAIN (
10k
100k1M10M–60
FREQUENCY (Hz)
Figure 10. Gain vs. Frequency vs. Code, RAB = 5 kΩ
10k
100k1M10M–60
GAIN (
FREQUENCY (Hz)
Figure 11. Gain vs. Frequency vs. Code, RAB = 10 kΩ
10k
100k1M10M–60
GAIN (
FREQUENCY (Hz)
Figure 12. Gain vs. Frequency vs. Code, RAB = 50 kΩ
10k
100k1M10M–60
GAIN (
FREQUENCY (Hz)
Figure 13. Gain vs. Frequency vs. Code, RAB = 100 kΩ
10k
100k1M10M–60
GAIN (
FREQUENCY (Hz)
Figure 14. –3 dB Bandwidth @ Code = 0x80
FREQUENCY (Hz)
10k100k1M0
03875-0-033
Figure 15. IDD vs. Frequency
VBIAS (V)
180
12000.51.01.52.02.53.03.54.04.55.05.5
Figure 16. RWB vs. VBIAS vs. VDD
CLK
1µs/DIV
Figure 17. Digital Feedthrough
200ns/DIV
Figure 18. Midscale Glitch, Code 0x40 to 0x3F
40µs/DIV
Figure 19. Large Signal Settling Time
TEST CIRCUITS
Figure 20 to define the test conditions used in the
product Specification tables.
Figure 24
03875-0-004
Figure 20. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
03875-0-009
∆VMS%
DD%PSS (%/%) = = VDD10%
PSRR (dB) = 20 LOGMS( )∆V
Figure 21. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
2.5V
+15V
VOUT
VIN
03875-0-010
Figure 22. Test Circuit for Gain vs. Frequency
VDD TO GND
DUT
RSW=0.1V
ISW
0.1V
Figure 23. Test Circuit for Incremental ON Resistance
NO CONNECT
Figure 24. Test Circuit for Common-Mode Leakage Current
