ADADC84-12 ,FAST, COMPLETE 12-BIT A/D CONVERTERSspecifications) LO . . . . mA
Tempco of Drift, (max) 120/max t 10 typ t5 typ 15 typ AIO ppm/"C
PO ..
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4. The internal buried zener reference is l ..
ADADC85SZ-12 ,Fast, Complete 12-Bit A/D Convertersapplications, and the input buffer amplifier add flexibility and value. All digital signals are ful ..
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ADSP-BF532SBBZ400 ,400 MHz High Performance Blackfin ProcessorFEATURESSDRAM, SRAM, FLASH, and ROMUp to 600 MHz high performance Blackfin processor Flexible memor ..
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AD5240KD-AD5240SD-ADADC84-12-ADADC85C-12
FAST, COMPLETE 12-BIT A/D CONVERTERS
ANALOG
DEVICES
Fast, Complete
12-Bit A/D Converters
AD MOM/M ADCB5/A05240
FEATURES
Performance
Complete 12-Bit AID Converter with Reference and Clock
Fast Successive Approximation Conversion: 10ps or 5ps
Buried Zener Reference for Long Term Stability and Low
Gain T.C.: 10ppml°c
Max Nonlinearity: <30.012%
Low Power: 880mW Typical
Low Chip Count - High Reliability
Industry Standard Pin Out
"2" Models for 112V Operation Available
MlL-STD-8838 Processing Available
Versatility
Nagative-True Parallel or Serial Logic Outputs
Short Cycle Capability
Precision +6.3V Reference for External Applications
PRODUCT DESCRIPTION
The AD ADC84/AD ADC85/AD5240 series devices are high-
speed, low-cost 10- and 12-bit successive approximation
analog-to-digital converters that include internal clock, refer-
ence and comparator. Its hybrid IC design utilizes MSI digital
and linear monolithic chips in conjunction with a Ibbit
monolithic DAC to provide modular performance and versa-
tility with IC size, price and reliability.
Important performance characteristics of the AD ADC84/
AD ADCBS/ADS 240 series include a maximum linearity error
at +25°c of $001296, gain T.C. below 15ppm/°C. typical
power dissipation of 880mW, and conversion time of less than
10ps for the 12-bit versions. Of considerable significance in
severe and aerosgace applications is the guaranteed perfor-
mance from -55 c to +125°c of the AD ADC85S which is
also available with environmental screening. Monotonic
operation of the feedback D/A converter guarantees no
. . O O
missmg> codes ovfLt5mper_afhr,e, ranges of o to +70 C, -25 C
to +85 C, and -55 C to +125 C.
The design of the AD ADC84/AD ADC85/AD5240 includes
scaling resistors that provide analog input signal ranges of
$2.5, i5. -+10, o to +5, or o to +10 volts. Adding flexibility
and value are the +6.3V precision reference, which also can
be used for external applications, and the input buffer ampli-
fier. All digital signals are fully DTL and TTL compatible,
and the data output is negative-true and available in either
serial or parallel form.
The AD ADC84/AD ADC85/AD5240 series devices are avail-
able in two different performance grades. The devices are
specified for either 10-bit accuracy ($004896 FSR max) or
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
AD ADC8WAD ADcteVA0S24tt
(Lsa FOR 'ZBITS) SERIAL Out
BIT 11 BUFFER MiN SUFFLY
ILSB FOR 10 MTS) A BUFFER IN
BIT t) BUFFER DUT
BIT! 'MN SWPLV
BIT 7 GAIN ADJUST
ANALOG
BIT G GROUND
MT s SPAN INPUT
SPAN INPUT
53" 23 BIPOLAR
OFFSET
22 Y'""'"
IZSIT D/A
MT a CONVERTER
cONVERT
mr ' COMMAND
am REFERENCE STATUS
CYCLE CLOCK DUT
DIGITAL
HN SKA'PLY
REF OUT 6.3V
GATED CLOCK
l CONYROI- CLOCK BATE
CIHEUITS CONTROL
12-bit accuracy (-+0.012% FSR max) with 8.4ps, 10ps
(AD ADC84/AD ADC85) and 4.1m, Sus (AD5240) max
conversion times respectively.
The AD ADC84 and AD ADC85C specified for operation over
the 0 to +70°C temperature range. The AD ADC85 and
AD ADCMS are specified for the -2 5°C to +85°C, -ss°c to
+125°C ranges respectively.
PRODUCT HIGHLIGHTS
1. The AD ADC84/AD ADC85/AD5 240 series devices are
complete 12-bit A/D converters. No external components
are required to perform a conversion.
2. The AD ADC84/AD ADC85/AD5240 directly replaces
other devices of this type with significant increases in
performance.
3. The fast conversion rates of the AD ADC84/AD ADC85
(10ps) and AD5240 (lips) make them an excellent choice
for applications requiring high system throughput rates.
4. The internal buried zener reference is laser trimmed to
6.3V $0.196 and :thppm/oc typical T.C. The reference
is available externally and can provide up to lmA.
5. The integrated package construction provides high quality
and reliability with small size and weight.
6. The monolithic 12-bit feedback DAC is used for reduced
chip count and higher reliability.
7. The AD ADC85S/883B and AD524OSD/883B come
processed to MIL-STD-883, Class B requirements (see
ADI Military Products Databook).
One Technology Way, PO. Box 9106, NonNood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703 wa: 710/394-6577
Telex: 924491 Cable: ANALOG NORWOODMASS
M got 84/AD Jl0t85/h0524il-SPEillFliyfrla
(typical@ +25°c, t1511 and
+5V unless otherwise noted)
AD5240KD/
MODEL AD ADC84 AD ADCESC AD ADC85 AD ADC355 AD5240SD UNITS
RESOLUTION 10/12 10/12 10/12 10/12 12 Bits
ANALOG INPUTS
Voltage Ranges
Bipolar $2.5. M, 210 . . . . Volts
Unipolar 0 to +5, 0 to +10 . . . . Volts
Impedance (Direct Input)
ov " +5V. 12.5V 2.5(h20%) . . . . kit
0v to +1ov, MV $(t20%) . . . . m
110V 10(t2096) . . . . m
Buffer Amplifierl
Impedance (min) 100 . . . . MD
Bias Current 50 . . . . nA
Settling Time
To 0.01% for 20V Step 2 . . . . ps
DIGITAL INPUTS'
Convert Command Positive Pulse 100ns min Trailing
Edge Initiates Conversion . . . t
lagic Loading 1 . . . . TTL Load
TRANSFER CHARACTERISTICS ERROR
Gain Error3 +-thlit0.25% max) . . . t0.2 91.
Offset Errors Adjustable to Zero . . . .
Unipolar 10.05(t0.2% max) . . . $0.1 as of FSR'
Bipoiars :0.1(:0.25% max) . . . 10.2 as of FSR
Linearity Error (maxf 10.048/10.012 . . . *0,012 96 of FSR
Inherent Quantization Error 10.5 . . . . LSB
Differential Linearity Error 10.5 . . . . LSB
No Missing Codes Temperature Range o to +70 0 to +70 -25 to +85 -55 to +125 o to +70/-55 to +125 "c
Power Supply Sensitivity
AISV 10.004 . . . . % of FSR/Mr
+5V $0.001 . . . . % of FSR/%V
Specification Temperature Range 0 to +70 . -25 to +85 -0 to +125 o to +70/-55 to +125 "c
Gain (max) 130 140/225 120/115 t25 30/125 ppm/°C
Offset
Unipoiar 13 . . M max . ppm/"C
Bipolar tmax)' 115 120/212 210/27 :10 215/:7 ppmfc
Linearity (max) t3 . 13/i2 . 12 ppme
Monotonicity GUARANTEED . . . GUARANTEED
GJNVERSION SPEED (MAX) 8.4/10 . . . 5 us
DIG ITAL OUTPUT
(xll codes complementary)
Parallel
Output Codes'
Unipolar CSB . . . .
Bipolar COB, cr C ' . . .
Output Drive 2 . . . . TTL Loads
Serial Data Codes (NR2) CSB, COB . . . .
Output Drive 2 . . . . TTL Loads
Status Logic "I" during Conversion . . . .
Status Output Drive 2 . . . . TTI. Loads
Internal Clock
Clock Output Drive 2 . . . . TTL Loads
Frequency 1.9/1.22 . . . 2.6 MHz
INTERNAL REFERENCE VOLTAGE 6.3/115mV max . . . . Volts
Max. External Current (with no
degradation of specifications) 1.0 . . . . mA
Tempco of Drift, (max) MO/max AIO typ 15 typ t5 typ 110 ppm/° C
POWER REQUIREMENTS
Rated Voltages Hi, 115 . . . . Volts
Range for Rated Accuracy 4.75 to 5.25 and $13.5 to 116.5 . . . . Volts
E Models' 4.75 to 5.25 and 111.4 to 116.5 . . . . Volts
Supply Drain t15V M max . . . 15 max mA
-15V " max . . . 35max mA
+5V 140 max . . . 100 max mA
Total Power Dissipation 1500 max . . . 1100 max mW
TEMPERATURE RANGE
Specirusrion 0 to +70 . -2s to +85 -5s to +125 0 to +70/-55 to +125 "c
Operating (Derated Specs) -25 to +85 . -55 to +125 -55 to +125 -55 to +125 °C
Storage -55 to #125 . . . -65 to +150 "c
PACKAGE OPTION'
DlI-32F Ceramic Ceramic Ceramic Ceramic Ceramic
'Butter Settling time adds to conversion speed when buffer is commend to input 'See Tune l.
'DTL/TI'L compatible Logic "O'' " 0.8V rmx. Logic "t" - 2.0V min for
digital output. Log}: "o" . 0.4V mu. Logic "C' I 2.4V min.
'Adjusuble to um.
'FSR mum Full Scale Range.
'Guaranteed " VIN " o volts.
'tirrorshows, isthesame.st1t2LSB mucrmrin xofFSR.
' For tt2V operation udd "Z" to model aumber. Input nag: limited to .
maximum of 25V.
'For p"kage outline information see Pucklge Information section.
'Specifications sum as AD ADC64.
speciracatiotts subject to clung: without nodcc.
REV. A
Typical Performance Curves - M ADCB4/AD A0il85/M5fl4tl
' '. _ Anna“
l TYPICAL DATA arc . I ADADCESCJ!
g 3 ADADCBEC-Iz
E s “a
' m \ g ADA068512
g " " MT "s, ii'
[i' \ QT 'i' AD Aucxss
s 's ‘~ o
2 llk\
o ' 2 3 4 5 s,'""" 1 I 9 " ,55 .15 o "s on us +15
couvensm TIME -t" TEMPERATURE -e
Figure M, Linearity Error vs. Conversion Speed Figure 3a. Gain Drift Error (% FSR) vs. Temperature
(AD ADC84/AD ADC85) (AD ADC84/AD A0085)
a V IZ-BIT OPERATION
i ( 'ss I
E m \ l
fl, l/IMIT OFEIAYION g
8-!" o-gi'." o
o , 2 , . ' B , ' Mi6 .25 o "gt,,,-, mi +15 +13.
CONVERSION TIME - us
Figure 1b. Linearity Error vs. Conversion Speed (AD5240) Figure 3b. Gain Drift Error (% FSR) vs. Temperature
(AD5240)
a I TS
gm. "l N,
' lzllTOPERATION
g \ \ l m N. (
g 1/: g
i ""\ mmx “A g 1)sssiss. J"'" OPERATION
E g "s, ,N
E m 'u,, 'u,, g "s, "sd "ss.,
it, \ 'sa... "ss, 8 5 f s--dC.C,'."rr-----.,
B45ITtPERATltm _
, 2 3 a 5 O 7 8 9 "
CONVERSION TIME - pl
Figure 2a. Change in Differential Linearity vs. Conversion -5 " " a cgm,du,',ua,,'" ”2 "“15
Speed (AD ADC84/AD ADC85)
Figure 4a. Conversion Speed vs. Control Voltage
, (AD ADC84/AD ADC85)
y-'"''' OPERATION
'ser opmnuon
k um OPERATION
128W MRATION
"MUT OPERATION
CONVERSION TIME — pk
DIFFERENTIAL LINEAR!" EIKDK - L“
$311 OPERATION
, 2 3 G 5 6 1 I " 0 2 4 5 3 I " " "
CONVERSION TIME - " CONTROL VOLTAGE ON PIN " - v
Figure 2b. Change in Differential Linearity vs. Conversion Figure 4b. Conversion Speed vs. Control Voltage
Speed (AD5240) (A05240)
REV. A .-3-
AD ADCB4/AD ADCB5/A0524l]
ORDERING GUIDE
Temperature Gain Conversion
Modelx Linearity Range T. C. - ppm/° C Time
AD ADC84-10 t0.048% 0 to +7o°c t30 10ps
AD ADC84-12 t0.012% O to +70°C Mo 10ps
AD ADC85C-10 10.04896 o to +70°C t40 10ps
AD ADC85C-12 10.01296 0 to +7o°c M5 mm
AD ADC85-10 i0.048% -250C to +85°C 120 10ps
AD ADC85-12 10.01296 -2f'c to +85°C t15 10ps
AD ADC85S-10 10.04896 -ss°c to +125°c t25 10ps
AD ADC85S-12 t0.012% -sy'c to +125°C fc25 lOps
AD5240KD t0.012% o t0 +7o°c Mo Sus
AD ADC858-12/883B M.012% -55°C to +125°C t25 10ps
AD524OSD/883B M.012% -55°C no +125°C k25 Sus
l For complete model number suffixes must be added 'Model Number Typical Part Numbers
for "Z" option (t12V operation), linearity. The “"2" Version Desigaator AD ADC84-12
following guide shows the proper suffix order. "'Linearity AD ADC8 552-1 2
AD ADC (')t"Vi"') AD524OZKD
OFFSET ADJ USTMENT
The zero adjust circuit consists of a potentiometer connected
across f-Vs with its slider connected through a 1.8MQ resistor
to Comparator input pin 22 for all ranges. As shown in Figure
5 the tolerance of this fixed resistor is not critical, and a car-
bon composition type is generally adequate. Using a carbon
composition resistor having a -1200ppm/°C tempco contributes
a worst-case offset tempco of 8X 244X 10" X 1200ppml°c =
2.3ppm/°C of FSR, if the OFFSET ADJ potentiometer is set
at either end of its adjustment range. Since the maximum off-
set adjustment required is typically no more than $41.58, use
of a carbon composition offset summing resistor typically con-
tributes no more than 1ppm/°C of FSR offset tempco.
Figure 5. Offset Adjustment Circuit
An alternate offset adjust circuit, which contributes negli-
gible offset tempco if metal film resistors (tempco <100
ppm/°C) are used, is shown in Figure 5.
AD Aocs4/
a AD ADCSS/
ADS240
180ki2 M.F. 180ktt M.F.
Figure 6. Low Tempco Zero Adjustment Circuit
In either zero adjust circuit, the fixed resistor connected to
pin 22 should be located close to this pin to keep the pin
connection runs short (Comparator Input pin 22 is quite
sensitive to external noise pick-up).
GAIN ADJ USTMENT
The gain adjust circuit consists of a potentiometer connected
across tVs with its slider connected through a 10M!) resistor
to the gain adjust pin 27 as shown in Figure 7.
Figure 7. Gain Adjustment Circuit
An alternate gain adjust circuit which contributes negligible
gain tempco if metal film resistors (Tempco < lOOppm/°C)
are used is shown in Figure 8.
AD ADCS4/
AD ADC85/
A05240
Figure 8. Low Tempco Gain Adjustment Circuit
M- REV. A
Applying the M ADCB4/AD AOM5/M524il
THEORY OF OPERATION
On receipt of a CONVERT START command, the AD ADC84/
AD ADC85/AD5240 converts the voltage as its analog input
into an equivalent 12-bit binary number. This conversion is
accomplished as follows: the 12-bit successive-approximation
register (SAR) has its 12-bit outputs connected both to the
device bit output pins and to the corresponding bit inputs of
the feedback DAC. The analog input is successively compared
to the feedback DAC output, one bit at a time (MSB first,
LSB last). The decision to keep or reject each bit is then
made at the completion of each bit comparison period,
depending on the state of the comparator at that time.
TIMING
The timing diagram is shown in Figure 9. Receipt of a CON-
VERT START signal sets the STATUS flag, indicating conver-
sion in progress. This, in turn, removes the inhibit applied to
the gated clock, permitting it to run through 13 cycles. All the
SAR parallel bits, STATUS flip-flops, and the gated clock
inhibit signal are initialized on the trailing edge of the
CONVERT START signal. At time to, Bt is reset and Ba -
CONVERT'
INTERNAL
STATUS
BIT 10
BIT 11
SERIAL
DATA OUT
REV. A
B12 are set unconditionally. At tt the Bit 1 decision is made
(keep) and Bit 2 is unconditionally reset. At t2, the Bit 2
decision is made (keep) and Bit 3 is reset unconditionally.
This sequence continues until the Bit 12 (LSB) decision (keep)
is made at ti2. After a 40ns delay period, the STATUS flag is
reset, indicating that the conversion is complete and that the
parallel output data is valid. Resetting the STATUS flag re-
stores the gated clock inhibit signal, forcing the clock output
to the Logic "o'' state.
Corresponding serial and parallel data bits become valid on
the same positivegoing clock edge. Serial data does not change
and is guaranteed valid on negative-going clock edges, however;
serial data can be transferred quite simply by clocking into a
receiving shift register on these edges (see Figure 9).
Incorporation of this 40ns delay guarantees that the parallel
(and serial) data are valid at the Logic "I'' to "O" transition
of the STATUS flag, permitting-parallel data transfer to be
initiated by the trailing edge of the STATUS signal.
Fr------- MAXIMUM THROUGHPUT TIME
I --------- CONVERSION TIME (2) -----l r
LTlflflflflfl, L] Ll LI LI L] U-UL-L
I l I I l I 7 I I
To T, T: IT: IT: ITS Te IT, lTa ITS Tu: T11
- (3) a e a a a . a a (4) T
:::L "o" I I I I I "
- - - l t I I ' '
2:1 I I I I I I I I I I I
-- -J |_l"1" l
:221___l "ty' f-"
ICC) l |"0" l I I I
- _, I
CLLI |_|"1" l l
rs-l l lu1n I I I
___J |_T'1" l
- l l "O'' n
---J |_i"1" l
-....1 1_|“1"
- -l MSB L non
"CngaaMi2'r-z-r3-Lscsjs,t7s,tscc-LLf'iBggggr,
lil'" M" "1.. 'T'' 'T" "I" "O'' "I" ''0" "I" "1., "O''
NOTES .
1. THE CONVERT START PULSE WIDTH Is 100ns MIN AND MUST REMAIN LOW DURING
A CONVERSION. THE CONVERSION IS INITIATED BY THE "TRAILING EDGE" OF THE
CONVERT COMMAND.
2. 10us FOR 12 BITS AND 8.4ws FOR 10 BITS (AD ADC84/AD A0085) OR6ws FOR 12 BITS
AND 4.1 ps FORM BITS (AD5240).
. MSB DECISION.
. LSB DECISION 20ns PRIOR TO THE STATUS GOING LOW.
''BIT DECISIONS.
Figure a Timing Diagram (Binary Code o 1 l 0 t 1 7 1 0 1 l 0)
