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AD5235BRU250
Nonvolatile Memory, Dual 1024 Position Digital Potentiometers
PRELIMINARY TECHNICAL DATA Nonvolatile Memory, Dual 1024
Position Digital Potentiometers
FEATURES Dual, 1024 Position Resolution
25K, 250K Ohm Terminal Resistance with 50ppm/°C Tempco
Nonvolatile Memory Preset
SPI Compatible Serial Data Input with Readback Function
Increment/Decrement Commands, Push Button Command
+3 to +5V Single Supply Operation
±2.5V Dual Supply Operation
30 bytes of general purpose nonvolatile memory
APPLICATIONS Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage to Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Power Supply Adjustment
DIP Switch Setting
GENERAL DESCRIPTION The AD5235 provides a dual channel, digitally controlled variable
resistor (VR) with resolutions of 1024 positions. These devices
perform the same electronic adjustment function as a potentiometer or
variable resistor. The AD5235’s versatile programming via a Micro
Controller allows multiple modes of operation and adjustment.
In the direct program mode a predetermined setting of the RDAC
register can be loaded directly from the micro controller. Another key
mode of operation allows the RDAC register to be refreshed with the
setting previously stored in the EEMEM register. When changes are
made to the RDAC register to establish a new wiper position, the
value of the setting can be saved into the EEMEM by executing an
EEMEM save operation. Once the settings are saved in the EEMEM
register, these values will be transferred automatically to the RDAC
register to set the wiper position at system power ON. Such operation
is enabled by the internal preset strobe and the preset can also be
accessed externally.
An internal scratch pad RDAC register can be programmed by the
micro controller to set the resistance between terminals W-and-B.
Once the target value is achieved, the RDAC content register can be
placed in the non-volatile memory for automatic recall during Power
Up.
The AD5235 is available in the thin TSSOP-16 package. All parts are
guaranteed to operate over the extended industrial temperature range
of -40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAMS PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5235
ELECTRICAL CHARACTERISTICS 25K, 250K OHM VERSIONS (VDD = +3V±10% or +5V±10% and VSS=0V, VA = +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)
Parameter Symbol Conditions Min Typ1 Max Units
PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5235
ELECTRICAL CHARACTERISTICS 25K, 250K OHM VERSIONS (VDD = +3V±10% to +5V±10% and VSS=0V, VA = +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)
Parameter Symbol Conditions Min Typ1 Max Units NOTES:
1. Typicals represent average readings at +25°C and VDD = +5V.
2. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step
change from ideal between successive tap positions. Parts are guaranteed monotonic. See figure 20 test circuit. IW = VDD/R for both VDD=+3V or VDD=+5V.
3. INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V. DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions. See Figure 19 test circuit.
4. Resistor terminals A,B,W have no limitations on polarity with respect to each other.
5. Guaranteed by design and not subject to production test.
6. PDISS is calculated from (IDD x VDD=+5V).
7. All dynamic characteristics use VDD = +5V.
8. See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2.5ns(10% to 90% of 3V) and timed from a voltage level of 1.5V. Switching characteristics are
measured using both VDD = +3V or +5V.
9. Propagation delay depends on value of VDD, RPULL_UP, and CL see applications text.
10. Low only for commands 8, 9,10, 2, 3: CMD_8 ~ 1ms; CMD_9,10 ~0.1ms; CMD_2,3 ~20ms.
Timing Diagram
CLK
SDI
SDO1
RDYSDO2
SDO1 CLK IDLES LOWSDO2 CLK IDLES HIGHFigure 1. Timing Diagram
PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5235
Absolute Maximum Rating (TA = +25°C, unless otherwise
noted)
VDD to GND..............................................................-0.3, +7V
VSS to GND.................................................................0V, -7V
VDD to VSS.........................................................................+7V
VA, VB, VW to GND.................................................VSS, VDD X – BX, AX – WX, BX – WX......................................±20mA
Ox to GND...................................................................0V, VDD
Digital Inputs & Output Voltage to GND..................0V, +7V
Operating Temperature Range.........................-40°C to +85°C
Maximum Junction Temperature (TJ MAX)...................+150°C
Storage Temperature.....................................-65°C to +150°C
Lead Temperature (Soldering, 10 sec)..........................+300°C
Thermal Resistance θJA,
TSSOP-16......................................................180°C/W
Package Power Dissipation = (TJMAX - TA) / θJA
Ordering Guide
The AD5235 contains 16,000 transistors.
Die size: 100 x 105 mil = 10,500 sq. mil
AD5235 PIN CONFIGURATION
CLK
SDI
SDO
GND
VSS
A1
W1
B1
RDY CS CS CS CS PRPRPR WPWPWP
VDD
A2
W2
B2
AD5235 PIN FUNCTION DESCRIPTION # Name Description CLK Serial Input Register clock pin. Shifts in one bit at
a time on positive clock edges. SDI Serial Data Input Pin. Shifts in one bit at a time
on positive clock CLK edges. SDO Serial Data Output Pin. Open Drain Output
requires external pull-up resistor. Commands 9
and 10 activate the SDO output. See Instruction
operation Truth Table. Table 2. GND Ground pin, logic ground reference
5 VSS Negative Supply. Connect to zero volts for single
supply applications. A1 A terminal of RDAC1. W1 Wiper terminal of RDAC1,
ADDR(RDAC1) = 0H. B1 B terminal of RDAC1. B2 B terminal of RDAC2.
10 W2 Wiper terminal of RDAC2,
ADDR(RDAC3) = 1H.
11 A2 A terminal of RDAC2.
12 VDD Positive Power Supply Pin. Should be ≥ the
input-logic HIGH voltage.
13 WP Write Protect Pin. Prevents any changes to the
present EEMEM contents when active low.
14 PR Hardware over ride preset pin. Refreshes the
scratch pad register with current contents of the
EEMEM register. Factory default loads midscale
51210.
15 CS Serial Register chip select active low. Serial
register operation takes place when CS returns to
logic high.
16 RDY Ready. Active-high open drain output. Identifies
completion of commands 2, 3, 8, 9, 10.
PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5235
OPERATIONAL OVERVIEW The AD5235 digital potentiometer is designed to operate as a true
variable resistor replacement device for analog signals that remain
within the terminal voltage range of VSS
voltage range is limited to a VDD - VSS<5.5V. Control of the digital
potentiometer allows both scratch pad register (RDAC register)
changes to be made, as well as 100,000 times of nonvolatile
electrically erasable memory (EEMEM) register operations. The
EEMEM update process takes approximately 20.2ms, during this
time the shift register is locked preventing any changes from taking
place. The RDY pin flags the completion of this EEMEM save.
The EEMEM retention is designed to last 10 years without refresh.
The scratch pad register can be changed incrementally by using the
software controlled Increment/Decrement instruction or the Shift
Left/Right instruction command. Once an Increment, Decrement or
Shift command has been loaded into the shift register, subsequent
CS strobes will repeat this command. This is useful for push button
control applications. Alternately the scratch pad register can be
programmed with any position value using the standard SPI serial
interface mode by loading the representative data word. The
scratch pad register can be loaded with the current contents of the
nonvolatile EEMEM register under the program control. At system
power ON, the default value of the scratch pad memory is the value
previously saved in the EEMEM register. The factory EEMEM
preset value is midscale 51210.
A serial data output pin is available for daisy chaining and for
readout of the internal register contents. The serial input data
register uses a 24-bit instruction/address/data WORD. The write-
protect (WP) pin provides a hardware EEMEM protection feature
disabling any changes of the present EEMEM contents.
SERIAL DATA INTERFACE
The AD5235 contains a four-wire SPI compatible digital interface
(SDI, SDO, CS, and CLK). Key features of this interface include: Independently Programmable Read & Write to all registers Direct parallel refresh of all RDAC wiper registers from
corresponding EEMEM registers Permanent storage of the present scratch pad RDAC register
values into the corresponding EEMEM register 30 bytes of user addressable electrical-erasable memory
The serial interface of AD5235 digital potentiometer uses a 24-bit
serial word loaded with MSB first. The format of the SPI
compatible word is shown in Table 1. The Command Bits (Cx)
control the operation of the digital potentiometer according to the
command instruction shown in Table 2. The Address Bits (Ax)
determine which register is activated. The Data Bits (Dx) are the
values that are loaded into the decoded register. The last
instruction executed prior to a period of no programming activity
should be the NOP instruction. This will place the internal logic
circuitry in a minimum power dissipation state.
CLKI
Figure 2. Equivalent Digital Input-Output Logic
The equivalent serial data input and output logic is shown in figure
2. The open drain output SDO is disabled whenever chip select CS
is logic high. The SPI interface can be used in two slave modes
CPHA=1, CPOL=1 and CPHA=0, CPOL=0. CPHA and CPOL
refer to the control bits, which dictate SPI timing in the following
microprocessors/MicroConverters: ADuC812/824, M68HC11, and
MC68HC16R1/916R1.
Table 1. AD5235 24-bit Serial Data Word
Command bits are identified as Cx, address bits are Ax, and data bits are Dx. Command instruction codes are defined in table 2.
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5235
Table 2. AD5235 Instruction/Operation Truth Table
NOTES:
1. The SDO output shifts-out the last 24-bits of data clocked into the serial register for daisy chain operation. Exception,
following Instruction #9 or #10 the selected internal register data will be present in data byte 0 & 1. Instructions following
#9 & #10 must be a full 24-bit data word to completely clock out the contents of the serial register.
2. The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding non-volatile
EEMEM register.
3. The increment, decrement and shift commands ignore the contents of the shift register Data Byte 0.
4. Execution of the Operation column noted in the table takes place when the CS strobe returns to logic high.
