AD5233BRU50 ,Nonvolatile Memory Digital PotentiometersGENERAL DESCRIPTION The AD5231/AD5232/AD5233 family provides a single-RDAC2SDO SDORDAC2A/dual-/quad ..
AD5235BRU250 ,Nonvolatile Memory, Dual 1024 Position Digital PotentiometersGENERAL DESCRIPTION The AD5235 provides a dual channel, digitally controlled variable resistor (VR ..
AD5235BRUZ250 , Nonvolatile Memory, Dual 1024-Position Digital Potentiometer
AD5240KD ,FAST, COMPLETE 12-BIT A/D CONVERTERSapplications, and the input buffer ampli-
fier. All digital signals are fully DTL and TTL compatib ..
AD5240SD ,FAST, COMPLETE 12-BIT A/D CONVERTERSCHARACTERISTICS ERROR
Gain Errors :0.1(:o.25% max) . . . 10.2 as
Offset Errors Adjustable to Zero ..
AD5241BR10 ,I2C® Compatible Digital PotentiometerCHARACTERISTICS (Applies to all parts. )SCL Clock Frequency f 0 400 kHzSCLt Bus Free Time between t ..
AD9000JD ,High Speed 6-Bit A/D ConverterCHARACTERISTICS unless otherwise noted)Commercial Military08C to +708C –558C to +1258CAD9000JD AD90 ..
AD9002AD ,High Speed 8-Bit Monolithic A/D ConverterGENERAL DESCRIPTIONBIT 2The AD9002 is an 8-bit, high speed, analog-to-digital converter.RThe AD9002 ..
AD9002AJ ,High Speed 8-Bit Monolithic A/D ConverterSpecifications subject to change without notice.–2– REV. DAD90021ABSOLUTE MAXIMUM RATINGS Recommend ..
AD9012AJ ,High Speed 8-Bit TTL A/D ConverterGENERAL DESCRIPTION D2The AD9012 is an 8-bit, ultrahigh speed, analog-to-digitalRD (LSB)converter. ..
AD9012AQ ,High Speed 8-Bit TTL A/D ConverterSpecifications subject to change without notice.1ABSOLUTE MAXIMUM RATINGSVSPositive Supply Voltage ..
AD9012BQ ,High Speed 8-Bit TTL A/D ConverterCHARACTERISTICS (+V = +5.0 V; –V = –5.2 V; Differential Reference Voltage = 2.0 V; unless otherwis ..
AD5233BRU50
Nonvolatile Memory Digital Potentiometers
PRELIMINARY TECHNICAL DATA a Nonvolatile Memory Digital Potentiometers
FEATURES Nonvolatile Memory Preset Maintains Wiper Settings
AD5231 Single, 1024 Position Resolution
AD5232 Dual, 256 Position Resolution
AD5233 Quad, 64 Position Resolution
10K, 50K, 100K Ohm Terminal Resistance
Linear or Log taper Settings
Increment/Decrement Commands, Push Button Command
SPI Compatible Serial Data Input with Readback Function
+3 to +5V Single Supply or ±2.5V Dual Supply Operation
User EEMEM nonvolatile memory for constant storage
APPLICATIONS Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage to Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Power Supply Adjustment
DIP Switch Setting
GENERAL DESCRIPTION The AD5231/AD5232/AD5233 family provides a single-
/dual-/quad-channel, digitally controlled variable resistor (VR)
with resolutions of 1024/256/64 positions respectively. These
devices perform the same electronic adjustment function as a
potentiometer or variable resistor. The AD523X’s versatile
programming via a Micro Controller allows multiple modes of
operation and adjustment.
In the direct program mode a predetermined setting of the
RDAC register can be loaded directly from the micro controller.
Another key mode of operation allows the RDAC register to be
refreshed with the setting previously stored in the EEMEM
register. When changes are made to the RDAC register to
establish a new wiper position, the value of the setting can be
saved into the EEMEM by executing an EEMEM save
operation. Once the settings are saved in the EEMEM register
these values will be transferred automatically to the RDAC
register to set the wiper position at system power ON. Such
operation is enabled by the internal preset strobe and the preset
can also be accessed externally.
The basic mode of adjustment is the increment and decrement
command controlling the present setting of the Wiper position
setting (RDAC) register. An internal scratch pad RDAC register
can be moved UP or DOWN, one step of the nominal terminal
resistance between terminals A-and-B. This linearly changes the
wiper to B terminal resistance (RWB) by one position segment of
the device's end-to-end resistance (RAB). For
exponential/logarithmic changes in wiper setting, a left/right
shift command adjusts levels in +/-6dB steps, which can be
useful for sound and light alarm applications.
The AD523X are available in the thin TSSOP package. All
parts are guaranteed to operate over the extended industrial
temperature range of -40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAMS CLK
SDI
SDO
VDD1
VSS2
RDY
GND
CLK
SDI
SDODD11SS
RDY
GND22
PRELIMINARY TECHNICAL DATA
AD5231/AD5232/AD5233 - SPECIFICATIONS
ELECTRICAL CHARACTERISTICS 10K, 50K, 100K OHM VERSIONS (VDD = +3V±10% or +5V±10% and VSS=0V, VA = +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)
Parameter Symbol Conditions Min Typ1 Max Units NOTES: See bottom of table next page.
PRELIMINARY TECHNICAL DATA
AD5231/AD5232/AD5233 - SPECIFICATIONS
ELECTRICAL CHARACTERISTICS 10K, 50K, 100K OHM VERSIONS (VDD = +3V±10% to +5V±10% and VSS=0V, VA = +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)
Parameter Symbol Conditions Min Typ1 Max Units NOTES:
1. Typicals represent average readings at +25°C and VDD = +5V.
2. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the
relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD=+3V or VDD=+5V.
3. INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = VSS. DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions.
4. Resistor terminals A, B, W have no limitations on polarity with respect to each other.
5. Guaranteed by design and not subject to production test.
6. Common mode leakage current is a measure of the DC leakage from any terminal A, B, W to a common mode bias level of VDD / 2.
7. PDISS is calculated from (IDD x VDD) + (ISS X VSS).
8. All dynamic characteristics use VDD = +5V.
9. See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2.5ns(10% to 90% of 3V) and timed from a voltage level of 1.5V. Switching
characteristics are measured using both VDD = +3V or +5V.
10. Propagation delay depends on value of VDD, RPULL_UP, and CL see applications text.
11. Low only for instruction commands 8, 9,10, 2, 3: CMD_8 ~ 1ms; CMD_9,10 ~0.12ms; CMD_2,3 ~20ms
12. Dual Supply Operation primarily affects the POT terminals.
13. Read Mode current is not continuous.
Timing Diagram
CLK
SDI
SDO1
RDYSDO2
SDO1 CLK IDLES LOWSDO2 CLK IDLES HIGHFigure 1. Timing Diagram
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
Absolute Maximum Rating (TA = +25°C, unless otherwise noted)
VDD to GND..............................................................-0.3, +7V
VSS to GND.................................................................0V, -7V
VDD to VSS.........................................................................+7V
VA, VB, VW to GND..................................................VSS, VDD
AX – BX, AX – WX, BX – WX
Intermittent...................................................±20mA
Continuous...................................................±1.3mA
Ox to GND..................................................................0V, VDD
Digital Inputs & Output Voltage to GND..................0V, +7V
Operating Temperature Range........................-40°C to +85°C
Maximum Junction Temperature (TJ MAX)..................+150°C
Storage Temperature.....................................-65°C to +150°C
Lead Temperature (Soldering, 10 sec).........................+300°C
Package Power Dissipation........................(TJMAX - TA) / θJA
Thermal Resistance θJA,
TSSOP-16.....................................................150°C/W
TSSOP-24.....................................................128°C/W
Ordering Guide
The AD5231/AD5232/AD5233 contains 9,646 transistors.
Die size: 69 mil x 115 mil, 7,993 sq. mil
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
AD5231 PIN CONFIGURATION
CLK
SDI
SDO
GND
VSS
RDYCSCSCSPRPRPRWPWPWP
VDD
AD5231 PIN FUNCTION DESCRIPTION # Name Description O1 Non-Volatile Digital Output #1, ADDR(O1) =
1H, data bit position D0 CLK Serial Input Register clock pin. Shifts in one
bit at a time on positive clock CLK edges. SDI Serial Data Input Pin. SDO Serial Data Output Pin. Open Drain Output
requires external pull-up resistor. Commands 9
& 10 activate the SDO output. See Instruction
operation Truth Table. Other commands shift
out the previously loaded bit pattern delayed
by 24 clock pulses. This allows daisy-chain
operation of multiple packages. GND Ground pin, logic ground reference.
6 VSS Negative Supply. Connect to zero volts for
single supply applications. T1 Used as digital input during factory test mode.
Leave pin floating or connect to VDD or VSS. B1 B terminal of RDAC1. W1 Wiper terminal of RDAC1,
ADDR(RDAC1) = 0H
10 A1 A terminal of RDAC1.
11 VDD Positive Power Supply Pin. Should be ≥ the
input-logic HIGH voltage.
12 WP Write Protect Pin. When active low WP
prevents any changes to the present contents
except retrieving EEMEM contents and
RESET.
13 PR Hardware over ride preset pin. Refreshes the
scratch pad register with current contents of
the EEMEM register. Factory default loads
midscale 200H until EEMEM loaded with a
new value by the user (PR is activated at the
rising logic high transition)
14 CS Serial Register chip select active low. Serial
register operation takes place when CS returns
to logic high.
15 RDY Ready. Active-high open drain output.
Identifies completion of commands 2, 3, 8, 9,
10.
16 O2 Non-Volatile Digital Output #2, ADDR(O2) =
1H, data bit position D1.
AD5232 PIN CONFIGURATION
CLK
SDI
SDO
GND
VSS
RDYCSCSCSPRPRPRWPWPWP
VDD
AD5232 PIN FUNCTION DESCRIPTION # Name Description CLK Serial Input Register clock pin. Shifts in one
bit at a time on positive clock edges. SDI Serial Data Input Pin. Shifts in one bit at a
time on positive clock CLK edges. SDO Serial Data Output Pin. Open Drain Output
requires external pull-up resistor. Commands 9
& 10 activate the SDO output. See Instruction
operation Truth Table. Other commands shift
out the previously loaded bit pattern delayed
by 16 clock pulses. This allows daisy-chain
operation of multiple packages. GND Ground pin, logic ground reference
5 VSS Negative Supply. Connect to zero volts for
single supply applications. A1 A terminal of RDAC1. W1 Wiper terminal of RDAC1,
ADDR(RDAC1) = 0H. B1 B terminal of RDAC1. B2 B terminal of RDAC2.
10 W2 Wiper terminal of RDAC2,
ADDR(RDAC2) = 1H.
11 A2 A terminal of RDAC2.
12 VDD Positive Power Supply Pin. Should be ≥ the
input-logic HIGH voltage.
13 WP Write Protect Pin. When active low, WP
prevents any changes to the present contents,
except retrieving EEMEM content and
RESET.
14 PR Hardware over ride preset pin. Refreshes the
scratch pad register with current contents of
the EEMEM register. Factory default loads
midscale 80H until EEMEM loaded with a new
value by the user (PR is activated at the logic
high transition).
15 CS Serial Register chip select active low. Serial
register operation takes place when CS returns
to logic high.
16 RDY Ready. Active-high open drain output.
Identifies completion of commands 2, 3, 8, 9,
10.
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
AD5233 PIN CONFIGURATION
CLK
SDI
SDO
GND
VSS
RDYCSCSCSPRPRPRWPWPWP
VDD
AD5233 PIN FUNCTION DESCRIPTION # Name Description O1 Non-Volatile Digital Output #1, ADDR(O1) = 4H, data bit position D0. CLK Serial Input Register clock pin. Shifts in one bit at a time on positive clock CLK edges. SDI Serial Data Input Pin. SDO Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands 9 & 10 activate the SDO output.
See Instruction operation Truth Table. Other commands shift out the previously loaded bit pattern delayed by 16 clock
pulses. This allows daisy-chain operation of multiple packages. GND Ground pin, logic ground reference
6 VSS Negative Supply. Connect to zero volts for single supply applications. A1 A terminal of RDAC1. W1 Wiper terminal of RDAC1, ADDR(RDAC1) = 0H. B1 B terminal of RDAC1.
10 A2 A terminal of RDAC2.
11 W2 Wiper terminal of RDAC2, ADDR(RDAC2) = 1H.
12 B2 B terminal of RDAC2.
13 B3 B terminal of RDAC3.
14 W3 Wiper terminal of RDAC3, ADDR(RDAC3) = 2H.
15 A3 A terminal of RDAC3.
16 B4 B terminal of RDAC4.
17 W4 Wiper terminal of RDAC4, ADDR(RDAC4) = 3H.
18 A4 A terminal of RDAC4.
19 VDD Positive Power Supply Pin. Should be ≥ the input-logic HIGH voltage.
20 WP Write Protect Pin. When active low, WP prevents any changes to the present contents, except retrieving EEMEM content
and RESET.
21 PR Hardware over ride preset pin. Refreshes the scratch pad register with current contents of the EEMEM register. Factory
default loads midscale 20H until EEMEM loaded with a new value by the user (PR is activated at the logic high
transition).
22 CS Serial Register chip select active low. Serial register operation takes place when CS returns to logic high.
23 RDY Ready. Active-high open drain output. Identifies completion of commands 2, 3, 8, 9, 10.
24 O2 Non-Volatile Digital Output #2, ADDR(O2) = 4H, data bit position D1.
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
OPERATIONAL OVERVIEW The AD5231/32/33 digital potentiometer family is designed to
operate as a true variable resistor replacement device for analog
signals that remain within the terminal voltage range of
VSS
VSS| < 5.5V.
Control of the digital potentiometer allows both scratch pad
register (RDAC register) changes to be made, as well as,
100,000 nonvolatile electrically erasable memory (EEMEM)
register operations. The EEMEM update process takes
approximately 20.2ms, during this time the shift register is
locked preventing any changes from taking place. The RDY pin
flags the completion of this EEMEM save. The EEMEM
retention is designed to last 15 years at 85°C, which is
equivalent to 90 years at 55°C, without refresh.
The scratch pad register can be changed incrementally by using
the software controlled Increment/Decrement instruction or the
Shift Left/Right instruction command. Once an Increment,
Decrement or Shift command has been loaded into the shift
register subsequent CS strobes will repeat this command. This is
useful for push button control applications. Alternately the
scratch pad register can be programmed with any position value
using the standard SPI serial interface mode by loading the
representative data word. The scratch pad register can be loaded
with the current contents of the nonvolatile EEMEM register
under program control. At system power ON, the default value
of the scratch pad memory is the value previously saved in the
EEMEM register. The factory EEMEM preset value is midscale.
The scratch pad (wiper) register can be loaded with the current
contents of the nonvolatile EEMEM register under hardware
control by pulsing the PR pin. Beware that the PR pulse first sets
the wiper at midscale when brought to logic zero, and then on
the positive transition to logic high, it reloads the DAC wiper
register with the contents of EEMEM. Similarly, the saved
EEMEM value will automatically be retrieved to the scratch pad
register during system power ON.
A serial data output pin is available for daisy chaining and for
readout of the internal register contents. The serial input data
register uses a 16 or 24-bit instruction/address/data WORD.
Write protect (WP) disables any changes of current content in
the scratch pad register regardless of the commands, except that
EEMEM setting can be retrieved using commands 1 and 9.
Therefore, write-protect (WP) pin provides hardware EEMEM
protection feature.
DIGITAL INPUT/OUTPUT CONFIGURATION
All digital inputs are ESD protected high input impedance that
can be driven directly from most digital sources. For PR and WP,
which are active at logic low, can be tied directly to VDD if they
are not being used.
The SDO and RDY pins are open drain digital outputs where
pull-up resistors are needed only if using these functions. A
resistor value in the range of 1k to 10k ohm optimizes the power
and switching speed trade off.
SERIAL DATA INTERFACE
The AD523X family contains a four-wire SPI compatible digital
interface (SDI, SDO, CS, and CLK). Key features of this
interface include: Independently Programmable Read & Write to all registers Direct parallel refresh of all RDAC wiper registers from
corresponding internal EEMEM registers Increment & Decrement instructions for each RDAC wiper
register Left & right Bit Shift of all RDAC wiper registers to
achieve 6dB level changes Nonvolatile storage of the present scratch pad RDAC
register values into the corresponding EEMEM register Extra bytes of user addressable electrical-erasable memory
The serial interface contains three different word formats to
support the single AD5231, dual AD5232, and the quad
AD5233 digital potentiometer devices. The AD5232 and
AD5233 use a 16-bit serial data word loaded MSB first, while
the AD5231 uses a 24-bit serial word loaded MSB first. The
format of the SPI compatible word is shown in Table 1 and 2.
The Command Bits (Cx) control the operation of the digital
potentiometer according to the command instructions shown in
Table 3, 4, and 5. The Address Bits (Ax) determine which
register is activated. The Data Bits (Dx) are the values that are
loaded into the decoded register. The last instruction executed
prior to a period of no programming activity should be the No
OPeration (NOP) instruction. This will place the internal logic
circuitry in a minimum power dissipation state.
CLKI
Figure 2. Equivalent Digital Input-Output Logic
The equivalent serial data input and output logic is shown in
figure 2. The open drain output SDO is disabled whenever chip
select CS is logic high. The SPI interface can be used in two
slave modes CPHA=1, CPOL=1 and CPHA=0, CPOL=0. CPHA
and CPOL refer to the control bits, which dictate SPI timing in
the following microprocessors/Micro Converters:
ADuC812/824, M68HC11, and MC68HC16R1/916R1.
