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AD5232BRU10-AD5232BRU100-AD5232BRU100-REEL7-AD5232BRU50
8-Bit Dual Nonvolatile Memory Digital Potentiometer
REV.0
8-Bit Dual Nonvolatile Memory
Digital Potentiometer
FEATURES
Nonvolatile Memory Preset Maintains Wiper Settings
Dual Channel, 256-Position Resolution
Full Monotonic Operation DNL < 1 LSB
10 k�, 50 k�, 100 k� Terminal Resistance
Linear or Log Taper Settings
Push-Button Increment/Decrement Compatible
SPI-Compatible Serial Data Input with Readback
Function
3 V to 5 V Single Supply or �2.5 V Dual Supply
Operation
14 Bytes of User EEMEM Nonvolatile Memory for
Constant Storage
Permanent Memory Write Protection
100-Year Typical Data Retention TA = 55�C
APPLICATIONS
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Power Supply Adjustment
DIP Switch Setting
GENERAL DESCRIPTIONThe AD5232 device provides a nonvolatile, dual-channel,
digitally controlled variable resistor (VR) with 256-position
resolution. These devices perform the same electronic adjust-
ment function as a potentiometer or variable resistor. The
AD5232’s versatile programming via a microcontroller allows
multiple modes of operation and adjustment.
In the direct program mode a predetermined setting of the RDAC
register can be loaded directly from the microcontroller.
Another key mode of operation allows the RDAC register to be
refreshed with the setting previously stored in the EEMEM
register. When changes are made to the RDAC register to estab-
lish a new wiper position, the value of the setting can be saved
into the EEMEM by executing an EEMEM save operation.
Once the settings are saved in the EEMEM register these values
will be automatically transferred to the RDAC register to set the
wiper position at system power ON. Such operation is enabled
by the internal preset strobe and the preset can also be accessed
externally.
All internal register contents can be read out of the serial data
output (SDO). This includes the RDAC1 and RDAC2 registers,
the corresponding nonvolatile EEMEM1 and EEMEM2 regis-
ters, and the 14 spare USER EEMEM registers available for
constant storage.
*Patent pending.
FUNCTIONAL BLOCK DIAGRAMThe basic mode of adjustment is the increment and decrement
command controlling the present setting of the Wiper position
setting (RDAC) register. An internal scratch pad RDAC register
can be moved UP or DOWN one step of the nominal terminal
resistance between terminals A and B. This linearly changes the
wiper to B terminal resistance (RWB) by one position segment of
the devices’ end-to-end resistance (RAB). For exponential/loga-
rithmic changes in wiper setting, a left/right shift command
adjusts levels in ±6 dB steps, which can be useful for audio and
light alarm applications.
The AD5232 is available in a thin TSSOP-16 package. All parts
are guaranteed to operate over the extended industrial tempera-
ture range of –40°C to +85°C. An evaluation board is available,
Part Number: AD5232EVAL.
Figure 1.Symmetrical RDAC Operation
AD5232–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS,10 k�, 50 k�, 100 k� VERSIONS
( VDD = 3 V � 10% or 5 V � 10% and VSS = 0 V, VA = +VDD, VB = 0 V, –40�C < TA < +85�C unless otherwise noted.)POTENTIOMETER DIVIDER MODE — Specifications Apply to All VRs
INTERFACE TIMING CHARACTERISTICS – Applies to All Parts
NOTESTypical parameters represent average readings at 25°C and VDD = 5 V.Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
postions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW ~ 50 μA @ VDD = 2.7 V and
IW ~400 μA @ VDD = 5 V for the RAB = 10 kΩ version, IW ~ 50 μA for the RAB = 50 kΩ and IW ~ 25 μA for the RAB = 100 kΩ version. See Figure 13.INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = VSS.DNL
specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 14.Resistor terminals A, B, W have no limitations on polarity with respect to each other. Dual Supply Operation enables ground-referenced bipolar signal adjustment.Guaranteed by design and not subject to production test.Common-mode leakage current is a measure of the dc leakage from any terminal A, B, W to a common-mode bias level of VDD/2.Transfer (XFR) Mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See TPC 9.PDISS is calculated from (IDD � VDD) + (ISS � VSS).All dynamic characteristics use VDD = +2.5 V and VSS=–2.5V unless otherwise noted.See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltagelevel
of 1.5 V. Switching characteristics are measured using both VDD = 3 V or 5 V.Propagation delay depends on value of VDD, RPULL_UP, and CL. See applications text.Valid for commands that do not activate the RDY pin.RDY pin low only for instruction commands 8, 9, 10, 2, 3, and the PR hardware pulse: CMD_8 ~ 1 ms; CMD_9,10 ~ 0.12 ms; CMD_2,3 ~ 20 ms. Device operation
at TA = –40°C and VDD < 3 V extends the save time to 35 ms.Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at VDD = 2.7 V, TA = –40°C to +85°C, typical endurance at 25°C is
AD5232
AD5232Figure 2a.CPHA = 1 Timing Diagram
CLK
CPOL = 0SDOSDI
RDY
CPHA = 0
*NOT DEFINED, BUT NORMALLY MSB OF CHARACTER JUST RECEIVED.
THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.Figure 2b.CPHA = 0 Timing Diagram
ORDERING GUIDE
*Line 1 contains ADI logo symbol and the data code YYWW, line 2 contains detail model number listed in this column.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5232 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1(TA = 25°C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –7 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 V
VA, VB, VW to GND . . . . . . . . . . . . .VSS– 0.3 V, VDD +0.3 V
AX – BX, AX – WX, BX – WX
Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±20 mA
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±2 mA
Digital Inputs and Output Voltage to
GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V
Operating Temperature Range3 . . . . . . . . . . .–40°C to +85°C
Maximum Junction Temperature (TJ Max) . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Package Power Dissipation . . . . . . . . . . . . .(TJ Max – TA)/�JA
Thermal Resistance Junction-to-Ambient �JA,
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150°C/W
Thermal Resistance Junction-to-Case �JC,
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28°C/W
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Maximum terminal current is bounded by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the A, B, and W terminals at a given resistance.
3Includes programming of nonvolatile memory.
AD5232
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
OPERATIONAL OVERVIEWThe AD5232 digital potentiometer is designed to operate as a
true variable resistor replacement device for analog signals that
remain within the terminal voltage range of VSS < VTERM < VDD.
The basic voltage range is limited to a |VDD – VSS| < 5.5 V. The
digital potentiometer wiper position is determined by the RDAC
register contents. The RDAC register acts as a scratch pad,
register allowing as many value changes as necessary to place the
potentiometer wiper in the correct position. The scratch pad
register can be programmed with any position value using the
standard SPI serial interface mode by loading the complete
representative data word. Once a desirable position is found,
this value can be saved into a corresponding EEMEM register.
Thereafter the wiper position will always be set at that position
for any future ON-OFF-ON power supply sequence. The
EEMEM save process takes approximately 25 ms, during this
time the shift register is locked preventing any changes from
taking place. The RDY pin indicates the completion of this
EEMEM save.
SCRATCH PAD AND EEMEM PROGRAMMINGThe scratch pad register (RDAC register) directly controls the
position of the digital potentiometer wiper. When the scratch
pad register is loaded with all zeros, the wiper will be connected
to the B-Terminal of the variable resistor. When the scratch pad
register is loaded with midscale code (1/2 of full-scale position),
the wiper will be connected to the middle of the variable resis-
tor. And when the scratch pad is loaded with full-scale code, all
1s, the wiper will connect to the A-Terminal. Since the scratch
pad register is a standard logic register, there is no restriction on
the number of changes allowed. The EEMEM registers have a
program erase/write cycle limitation described in the Flash/
EEMEM Reliability section.
BASIC OPERATIONThe basic mode of setting the variable resistor wiper position
(programming the scratch pad register) is accomplished by
loading the serial data input register with the command instruc-
tion #11, which includes the desired wiper position data. When
the desired wiper position is found, the user loads the serial data
input register with the command instruction #2, which copies
the desired wiper position data into the corresponding nonvola-
tile EEMEM register. After 25 ms the wiper position will be
permanently stored in the corresponding nonvolatile EEMEM
location. Table I provides an application-programming example
listing the sequence of serial data input (SDI) words and the
corresponding serial data output appearing at the SDO pin in
hexadecimal format.
At system power-on, the scratch pad register is refreshed with
the value last saved in the EEMEM register. The factory preset
EEMEM value is midscale. The scratch pad (wiper) register can
be refreshed with the current contents of the nonvolatile
EEMEM register under hardware control by pulsing the PR pin.
Table I.Set Two Digital POTs to Independent Data Values
then Save Wiper Positions in Corresponding Nonvolatile
EEMEM RegistersBe aware that the PR pulse first sets the wiper at midscale when
brought to logic zero, and then on the positive transition to logic
high, it reloads the DAC wiper register with the contents of
EEMEM. Many additional advanced programming commands
are available to simplify the variable resistor adjustment process.
For example, the wiper position can be changed one step at a
time by using the software-controlled Increment/Decrement
instruction or, by 6 dB at a time, with the Shift Left/Right
instruction command. Once an Increment, Decrement, or Shift
command has been loaded into the shift register, subsequent CS
strobes will repeat this command. This is useful for push-button
control applications. See the Advanced Control Modes descrip-
tion following Table I. A serial data output SDO pin is
available for daisy chaining and for readout of the internal
register contents. The serial input data register uses a 16-bit
[instruction/address/data] WORD.
EEMEM PROTECTIONWrite protect (WP) disables any changes of the scratch pad
register contents regardless of the software commands, except
that the EEMEM setting can be refreshed using commands 8
and PR. Therefore, the write-protect (WP) pin provides a hard-
ware EEMEM protection feature. Execute a NOP command
before returning WP to logic high.
DIGITAL INPUT/OUTPUT CONFIGURATIONAll digital inputs are ESD-protected high input impedance that
can be driven directly from most digital sources. PR and WP,
which are active at logic low, must be biased to VDD if they are
not being used. No internal pull-up resistors are present on any
digital input pins.
The SDO and RDY pins are open-drain digital outputs where
pull-up resistors are needed only if using these functions. A
resistor value in the range of 1 kΩ to 10 kΩ optimizes the power
and switching speed trade-off.
AD5232
SERIAL DATA INTERFACEThe AD5232 contains a 4-wire SPI-compatible digital interface
(SDI, SDO, CS, and CLK), and uses a 16-bit serial data word
loaded MSB first. The format of the SPI-compatible word is
shown in Table II. The chip select (CS) pin needs to be held
low until the complete data word is loaded into the SDI pin.
When CS returns high, the serial data word is decoded accord-
ing to the instructions in Table III. The Command Bits (Cx)
control the operation of the digital potentiometer. The Address
Bits (Ax) determine which register is activated. The Data Bits
(Dx) are the values that are loaded into the decoded register.
Table IV provides an address map of the EEMEM locations.
The last instruction executed prior to a period of no program-
ming activity should be the No Operation (NOP) instruction.
This will place the internal logic circuitry in a minimum power
dissipation state.
Figure 3.Equivalent Digital Input-Output Logic
The equivalent serial data input and output logic is shown in
Figure 3. The open-drain output SDO is disabled whenever chip
select CS is logic high. The SPI interface can be used in two slave
modes CPHA = 1, CPOL = 1 and CPHA = 0, CPOL = 0.
CPHA and CPOL refer to the control bits, which dictate
SPI timing in these MicroConverters® and microprocessors:
ADuC812/ADuC824, M68HC11, and MC68HC16R1/916R1.
ESD protection of the digital inputs is shown in Figures 4a and 4b.
LOGIC
PINS
VDD
GNDFigure 4a.Equivalent ESD Digital Input Protection
VDD
GNDFigure 4b.Equivalent WP Input Protection
DAISY CHAINING OPERATIONThe serial data output pin (SDO) serves two purposes. It can
be used to read out the contents of the wiper setting and
EEMEM values using instruction 10 and 9 respectively. The
remaining instructions (#0–8, #11–15) are valid for daisy-
chaining multiple devices in simultaneous operations.
Daisy-chaining minimizes the number of port pins required
from the controlling IC (see Figure 5). The SDO pin contains
an open drain N-Channel FET that requires a pull-up resistor if
this function is used. As shown in Figure 5, users need to tie
the SDO pin of one package to the SDI pin of the next
package. Users may need to increase the clock period because
the pull-up resistor and the capacitive loading at the SDO-SDI
interface may require additional time delay between subsequent
packages. If two AD5232’s are daisy-chained, 32 bits of data
are required. The first 16 bits go to U2 and the second 16
bits with the same format go to U1. The 16 bits are formatted
to contain the 4-bit instruction, followed by the 4-bit address,
then the 8 bits of data. The CS should be kept low until all 32
bits are locked into their respective serial registers. The CS
is then pulled high to complete the operation.
Figure 5.Daisy-Chain Configuration Using SDO
Table II.16-Bit Serial Data Word
Table III.Instruction/Operation Truth Table
InstNOTES
1. The SDO output shifts out the last eight bits of data clocked into the serial register for daisy-chain operation. Exception: following Instruction #9 or #10 the selected internal
register data will be present in data byte 0. Instructions following #9 and #10 must be a full 16-bit data word to completely clock out the contents of the serial register.
2. The RDAC register is a volatile scratch pad register that is refreshed at power-on from the corresponding nonvolatile EEMEM register.
3. The increment, decrement, and shift commands ignore the contents of the shift register Data Byte 0.
4. Execution of the Operation column noted in the table takes place when the CS strobe returns to logic high.
5. Execution of a NOP instruction minimizes power dissipation.
AD5232Also the left shift commands were modified so that if the data in
the RDAC register is greater than or equal to midscale and the
data is left shifted then the data in the RDAC register is set to
full-scale. This makes the left shift function as close to ideally
logarithmic as is possible.
The right shift #4 and #5 commands will be ideal only if the
LSB is zero (i.e., ideal logarithmic–no error). If the LSB is a
one then the right shift function generates a linear half LSB
error, which translates to a code dependent logarithmic error
for odd codes only as shown in the attached plots, (see Figure
5). The plot shows the errors of the odd codes for the AD5232.
Figure 6.Detail Left and Right Shift Function for the
8-Bit AD5232
Actual conformance to a logarithmic curve between the data
contents in the RDAC register and the wiper position for each
Right Shift #4 and #5 command execution contains an error
only for the odd codes. Even codes are ideal except zero right
shift or greater than half-scale left shift. The graph in Figure 7
shows plots of Log_Error [i.e., 20 × log 10 (error/code)]. For
example, code 3 Log_Error = 20 × log 10 (0.5/3) = –15.56 dB,
which is the worst case. The plot of Log_Error is more signifi-
cant at the lower codes.
Figure 7.Plot of Log_Error Conformance for Odd Codes
Only (Even Codes Are Ideal)
ADVANCED CONTROL MODESThe AD5232 digital potentiometer contains a set of user program-
ming features to address the wide applications available to these
universal adjustment devices. Key programming features include:
Independently Programmable Read and Write to all registers.Simultaneous refresh of all RDAC wiper registers from
corresponding internal EEMEM registers.Increment and Decrement instructions for each RDAC wiper
register.Left and right bit shift of all RDAC wiper registers to achieve
6 dB level changes.Nonvolatile storage of the present scratch pad RDAC register
values into the corresponding EEMEM register.Fourteen extra bytes of user-addressable electrical-erasable memory.
Increment and Decrement CommandsThe increment and decrement commands (#14, #15, #6, #7)
are useful for the basic servo adjustment application. This com-
mand simplifies microcontroller software coding by eliminating
the need to perform a readback of the current wiper position,
then add one to the register contents using the microcontroller’s
adder. The microcontroller simply sends an increment command
(#14) to the digital POT, which will automatically move the
wiper to the next resistance segment position. The master incre-
ment command (#15) will move all POT wipers by one position
from their present position to the next resistor segment position.
The direction of movement is referenced to Terminal B. Thus
each increment #15 command will move the wiper tap position
farther away from Terminal B.
Logarithmic Taper Mode AdjustmentProgramming instructions allow a decrement and an increment
wiper position control by individual POT or in a ganged POT
arrangement where both wiper positions are changed at the
same time. These settings are activated by the 6 dB decrement
and 6 dB increment instructions #4 and #5 and #12 and #13
respectively. For example, starting with the wiper connected to
Terminal B executing nine increment instructions (#12) would
move the wiper in +6 dB steps from the 0% of RBA (B terminal)
position to the 100% of RBA position of the AD5232 8-Bit
potentiometer. The 6 dB increment instruction doubles the
value of the RDAC register contents each time the command is
executed. When the wiper position is greater than midscale, the
last 6 dB increment instruction will cause the wiper to go to the
Full-Scale 255 code position. Any additional +6 dB instruction
will no longer change the wiper position from full scale (RDAC
register code = 255).
Figure 6 illustrates the operation of the 6 dB shifting function
on the individual RDAC register data bits for the 8-bit AD5232
example. Each line going down the table represents a successive
shift operation. Very important: the left shift #12 and #13 com-
mands were modified so that if the data in the RDAC register is
equal to zero and the data is left shifted, it is then set to code 1.
