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AD5231BRU10-REEL7
Nonvolatile Memory, 1024-Position Digital Potentiometers
REV.0
Nonvolatile Memory,
1024-Position Digital Potentiometers
FUNCTIONAL BLOCK DIAGRAMFigure 1.RWA(D) and RWB(D) vs. Decimal Code
FEATURES
Nonvolatile Memory1 Preset Maintains Wiper Settings
1024-Position Resolution
Full Monotonic Operation
10 k�, 50 k�, and 100 k� Terminal Resistance
Permanent Memory Write-Protection
Wiper Settings Read Back
Linear Increment/Decrement
Log Taper Increment/Decrement
Push Button Increment/Decrement Compatible
SPI Compatible Serial Interface with Readback Function
3 V to 5 V Single Supply or �2.5 V Dual Supply
28 Bytes User Nonvolatile Memory for Constant Storage
100 Year Typical Data Retention TA = 55�C
APPLICATIONS
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage to Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Power Supply Adjustment
Low Resolution DAC Replacement
GENERAL DESCRIPTIONThe AD5231 provides nonvolatile memory digitally controlled
potentiometers2 with 1024-position resolution. These devices
perform the same electronic adjustment function as a mechanical
potentiometer. The AD5231’s versatile programming via a stan-
dard 3-wire serial interface allows 16 modes of operation and
adjustment, including scratch pad programming, memory stor-
ing and retrieving, increment/decrement, log taper adjustment,
wiper setting read back, and extra user-defined EEMEM.
In the scratch pad programming mode, a specific setting can be
programmed directly to the RDAC2 register, which sets the resis-
tance at terminals W-A and W-B. The RDAC register can also
be loaded with a value previously stored in the EEMEM1 regis-
ter. The value in the EEMEM can be changed or protected.
When changes are made to the RDAC register, the value of the
new setting can be saved into the EEMEM. Thereafter, such value
will be transferred automatically to the RDAC register during
system power ON. It is enabled by the internal preset strobe.
EEMEM can also be retrieved through direct programming and
external preset pin control.
Other operations include linear step increment and decrement
commands such that the setting in the RDAC register can be
moved UP or DOWN, one step at a time. For logarithmic changes
in wiper setting, a left/right bit shift command adjusts the level
in ±6 dB steps.
The AD5231 is available in thin TSSOP-16 package. All parts
are guaranteed to operate over the extended industrial tempera-
ture range of –40°C to +85°C.
NOTESThe terms Nonvolatile Memory and EEMEM are used interchangeably.The terms Digital Potentiometer and RDAC are used interchangeably.
*Patent pending
AD5231–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS 10 k�, 50 k�, 100 k� VERSIONS
(VDD = 3 V � 10% or 5 V � 10% and VSS = 0 V, VA = +VDD, VB = 0 V, –40�C < TA < +85�C, unless otherwise noted.)
AD5231NOTESTypicals represent average readings at 25�C and VDD = 5 V.Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. IW ~ 50 µA @ VDD = +2.7 V and IW ~ 400 µA @ VDD = +5 V for the RAB = 10 kΩ
version, IW ~ 50 �A for the RAB = 50 kΩ and IW ~ 25 �A for the RAB = 100 kΩ version. See test circuit Figure 12.INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = VSS. DNL
specification limits of –1 LSB minimum are Guaranteed Monotonic operating conditions. See test circuit Figure 13.Resistor terminals A, B, and W have no limitations on polarity with respect to each other. Dual Supply Operation enables ground-referenced bipolar signal adjustment.Guaranteed by design and not subject to production test.Common-mode leakage current is a measure of the dc leakage from any terminal B and W to a common-mode bias level of VDD/2.Transfer (XFR) Mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See TPC 19.PDISS is calculated from (IDD � VDD) + (ISS � VSS).All dynamic characteristics use VDD = +2.5 V and VSS = –2.5 V.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS 10 k�, 50 k�, 100 k� VERSIONSNOTESTypicals represent average readings at 25�C and VDD = 5 V.Guaranteed by design and not subject to production test.See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level
of 1.5V. Switching characteristics are measured using both VDD = 3 V and 5 V.Propagation delay depends on value of VDD, RPULL_UP, and CL. See applications text.Valid for commands that do not activate the RDY pin.RDY pin low only for commands 2, 3, 8, 9, 10, and the PR hardware pulse: CMD_8 ~ 1 �s; CMD_9,10 ~0.12 �s; CMD_2,3 ~20 �s. Device operation at TA = –40�C
and VDD < +3 V extends the save time to 35 �s.Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at –40�C, +25�C, and +85�C; typical endurance at 25�C is 700,000 cycles.Retention lifetime equivalent at junction temperature (TJ) = 55�C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV
will derate with junction temperature as shown in Figure 20 in the Flash/EE Memory Description section of this data sheet. The AD5231 contains 9,646 transistors.
Die size: 69 mil � 115 mil, 7,993 sq. mil.
(VDD = 3 V to 5.5 V and –40�C < TA < +85�C, unless otherwise noted.)
AD5231Figure 2a.CPHA = 1 Timing Diagram
Figure 2b.CPHA = 0 Timing Diagram
ABSOLUTE MAXIMUM RATINGS1(TA = 25°C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –7 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
VA, VB, VW to GND . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
A–B, A–W, B–W
Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Digital Inputs and Output Voltage to GND
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Operating Temperature Range3 . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (TJ Max) . . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Thermal Resistance Junction-to-Ambient �JA,
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W
Thermal Resistance Junction-to-Case �JC,
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28°C/W
Package Power Dissipation = (TJ Max – TA)/�JA
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.Maximum terminal current is bounded by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the A, B, and W terminals at a given resistance.Includes programming of nonvolatile memory
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5231 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE*Line 1 contains ADI logo symbol and the date code YYWW; line 2 contains detail model number listed in this column.
AD5231
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS6VSS
TPC 1.INL vs. Code, TA = –40°C, +25°C, +85°C Overlay,
RAB = 10 kΩ
TPC 2.DNL vs. Code, TA = –40°C, +25°C, +85°C Overlay,
RAB = 10 kΩ
TPC 3.R-INL vs. Code, TA = –40°C, +25°C, +85°C
TPC 4.R-DNL vs. Code, TA = –40°C, +25°C, +85°C
Overlay, RAB = 10 kΩ
TPC 5.�RWB/�T vs. Code, RAB = 10 kΩ
TPC 6.�RWB/�T vs. Code, RAB = 10 kΩ
AD5231TPC 7.Wiper-On Resistance vs. Code
TPC 8.IDD vs. Temperature, RAB = 10 kΩ
TPC 9.IDD vs. Clock Frequency, RAB = 10 kΩ
TPC 10.–3 Bandwidth vs. Resistance. Test Circuit in
Figure 16.
TPC 11.Total Harmonic Distortion vs. Frequency
TPC 12.Gain vs. Frequency vs. Code, RAB = 10 kΩ.
Test Circuit in Figure 18
TPC 13.Gain vs. Frequency vs. Code, RAB = 50 kΩ.
Test Circuit in Figure 18
TPC 14.Gain vs. Frequency vs. Code, RAB = 100 kΩ.
Test Circuit in Figure 18
TPC 15.PSRR vs. Frequency
VDD
0.5V/DIVTPC 16.Power-On Reset, VDD = 2.25 V,
Code = 1010101010B
TPC 17.Midscale Glitch Energy, Code 200H to 1FFH
TPC 18.IDD vs. Time (Save) Program Mode
AD5231
OPERATIONAL OVERVIEWThe AD5231 digital potentiometer is designed to operate as a
true variable resistor replacement device for analog signals that
remain within the terminal voltage range of VSS < VTERM < VDD.
The basic voltage range is limited to a |VDD – VSS| < 5.5 V. The
digital potentiometer wiper position is determined by the RDAC
register contents. The RDAC register acts as a scratch pad regis-
ter allowing as many value changes as necessary to place the
potentiometer wiper in the correct position. The scratch pad
register can be programmed with any position value using the
standard SPI serial interface mode by loading the complete repre-
sentative data word. Once a desirable position is found this value
can be saved into an EEMEM register. Thereafter the wiper
position will always be set at that position for any future ON-
OFF-ON power supply sequence. The EEMEM save process
takes approximately 25 ms, during this time the shift register is
locked preventing any changes from taking place. The RDY pin
indicates the completion of this EEMEM save.
There are 16 instructions that facilitate users’ programming
needs. Refer to Table III. The instructions are:Do NothingRestore EEMEM Setting to RDACSave RDAC Setting to EEMEMSave RDAC Setting or User Data to EEMEMDecrement 6 dBDecrement 6 dBDecrement One StepDecrement One StepReset EEMEM setting to RDAC
10.Read EEMEM to SDO
11.Read Wiper Setting to SDO
12.Write Data to RDAC
13.Increment 6 dB
Scratch Pad and EEMEM ProgrammingThe scratch pad register (RDAC register) directly controls the
position of the digital potentiometer wiper. When the scratch
pad register is loaded with all zeros, the wiper will be connected
to the B-Terminal of the variable resistor. When the scratch pad
register is loaded with midscale code (1/2 of full-scale position),
the wiper will be connected to the middle of the variable resistor.
And when the scratch pad is loaded with full-scale code, all ones,
the wiper will connect to the A-Terminal. Since the scratch pad
register is a standard logic register, there is no restriction on the
number of changes allowed. The EEMEM registers have a program
erase/write cycle limitation described in the Flash/EEMEM
Reliability section.
Basic OperationThe basic mode of setting the variable resistor wiper position
(programming the scratch pad register) is accomplished by
loading the serial data input register with the command instruc-
tion #11, which includes the desired wiper position data. When
the desired wiper position is found, the user would load the
serial data input register with the command instruction #2,
which makes a copy of the desired wiper position data into the
nonvolatile EEMEM register. After 25 ms the wiper position
will be permanently stored in the nonvolatile EEMEM location.
Table I provides an application-programming example listing
the sequence of serial data input (SDI) words and the serial data
output appearing at the SDO Pin in hexadecimal format.
Table I.Set and Save RDAC Data to EEMEM Register
CLK
SDI
IDD*
2mA/DIV
5V/DIV
5V/DIV
5V/DIV
* SUPPLY CURRENT RETURNS TO MINIMUM POWER CONSUMPTION
IF INSTRUCTION #0 (NOP) IS EXECUTED IMMEDIATELY AFTER
INSTRUCTION #1 (READ EEMEM)
4ms/DIVTPC 19.IDD vs. Time (Read) Program Mode
TPC 20.IWB_MAX vs. Code
During operation, the scratch pad (wiper) register can also be
refreshed with the current content of the nonvolatile EEMEM
register under hardware control by pulsing the PR Pin without
activating instruction 1 or 8. Beware that the PR pulse first sets
the wiper at midscale when brought to logic zero, and then on
the positive transition to logic high, it reloads the RDAC wiper
register with the contents of EEMEM. Many additional advanced
programming commands are available to simplify the variable
resistor adjustment process, See Table III. For example, the
wiper position can be changed one step at a time by using the
Increment/Decrement instruction or by 6 dB at a time with the
Shift Left/Right instruction command. Once an Increment, Decre-
ment, or Shift command has been loaded into the shift register,
subsequent CS strobes will repeat this command. This is useful
for push button control applications. See the advanced control
modes section following the Instruction Operation Truth Table. A
serial data output SDO Pin is available for daisy-chaining and
for readout of the internal register contents. The serial input
data register uses a 24-bit [instruction/address/data] WORD format.
EEMEM ProtectionWrite protect (WP) disables any changes of the scratch pad
register contents regardless of the software commands, except
that the EEMEM setting can be refreshed and overwritten WP
by using commands 1, 8, and PR pulse. Therefore, the write-
protect (WP) Pin provides a hardware EEMEM protection
feature. To disable WP, it is recommended to execute a NOP
command before returning WP to logic high.
Digital Input/Output ConfigurationAll digital inputs are ESD-protected high-input impedance that
can be driven directly from most digital sources. Active at logic
low, PR and WP must be biased to VDD if they are not used. No
internal pull-up resistors are present on any digital input pins.
The SDO and RDY Pins are open-drain digital outputs where
pull-up resistors are needed only if using these functions. A
resistor value in the range of 1 kΩ to 10 kΩ is a proper choice
which balances the power and switching speed trade off.
The equivalent serial data input and output logic is shown in
Figure 3. The open drain output SDO is disabled whenever chip
select CS is logic high. ESD protection of the digital inputs is
shown in Figures 4a and 4b.
Figure 3.Equivalent Digital Input-Output Logic
Figure 4a.Equivalent ESD Digital Input Protection
Figure 4b.Equivalent WP Input Protection
Serial Data InterfaceThe AD5231 contains a four-wire SPI compatible digital inter-
face (SDI, SDO, CS, and CLK). The AD5231 uses a 24-bit
serial data word loaded MSB first. The format of the SPI com-
patible word is shown in Table II. The chip select CS Pin needs
to be held low until the complete data word is loaded into the
SDI Pin. When CS returns high the serial data word is decoded
according to the instructions in Table III. The Command Bits
(Cx) control the operation of the digital potentiometer. The
Address Bits (Ax) determine which register is activated. The
Data Bits (Dx) are the values that are loaded into the decoded
register. Table V provides an address map of the EEMEM
locations. The last instruction executed prior to a period of no
programming activity should be the No Operation (NOP) instruc-
tion. This will place the internal logic circuitry in a minimum power
dissipation state.
The SPI interface can be used in two slave modes CPHA = 1,
CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer to
the control bits, that dictate SPI timing in these MicroConverters®
and microprocessors: ADuC812/ADuC824, M68HC11, and
MC68HC16R1/916R1.
Daisy-Chain OperationThe Serial Data Output Pin (SDO) serves two purposes. It can
be used to readout the contents of the wiper setting and EEMEM
values using instructions 10 and 9, respectively. The remaining
instructions (#0–#8, #11–#15) are valid for daisy-chaining
multiple devices in simultaneous operations. Daisy-chaining
minimizes the number of port pins required from the controlling IC
(see Figure 5). The SDO Pin contains an open drain N-Ch FET
that requires a pull-up resistor, if this function is used. As shown
in Figure 5, users need to tie the SDO Pin of one package to the
AD5231SDI Pin of the next package. Users may need to increase the clock
period because the pull-up resistor and the capacitive loading at
the SDO-SDI interface may require additional time delay between
subsequent packages. When two AD5231s are daisy-chained, 48
bits of data are required. The first 24 bits go to U2 and the second
24 bits go to U1. The 24 bits are formatted to contain the 4-bit
instruction, followed by the 4-bit address, 6-bit don’t care, then
the 10 bits of data. (The don’t care can be used to store user
information. See section Using Additional Internal Nonvolatile
EEMEM). The CS should be kept low until all 48 bits are clocked
into their respective serial registers. The CS is then pulled high to
complete the operation.
Figure 5.Daisy Chain Configuration using SDO
Terminal Voltage Operation RangeThe AD5231 positive VDD and negative VSS power supply
defines the boundary conditions for proper 3 terminal digital
potentiometer operation. Supply signals present on terminals A,
B, and W that exceed VDD or VSS will be clamped by the internal
forward biased diodes (see Figure 6).
The ground pin of the AD5231 device is primarily used as a
digital ground reference, which needs to be tied to the PCB’s
common ground. The digital input control signals to the AD5231
must be referenced to the device ground pin (GND), and satisfy
the logic level defined in the specification table of this data
sheet. An internal level-shift circuit ensures that the common-
mode voltage range of the three terminals extends from VSS to
VDD, regardless of the digital input level.
Figure 6.Maximum Terminal Voltages Set by VDD and VSS
Power-Up SequenceSince there are diodes to limit the voltage compliance at terminals
A, B, and W (see Figure 6), it is important to power VDD/VSS first
before applying any voltage to terminals A, B, and W. Otherwise,
the diode will be forward-biased such that VDD/VSS will be powered
unintentionally and may affect the rest of the user’s circuit. The
ideal power-up sequence is in the following order: GND, VDD, VSS,
Digital Inputs, and V A/B/W. The order of powering VA, VB, VW,
and digital inputs are not important as long as they are powered
after VDD/VSS.
Regardless of the power-up sequence and the ramp rates of the
power supplies, once VDD/VSS are powered, the power-on reset
remains effective, which retrieves EEMEM saved value to
RDAC register.
Latched Digital OutputsA pair of digital outputs, O1 and O2, is available on the AD5231
that provide a nonvolatile logic 0 or logic 1 setting. O1 and O2 are
standard CMOS logic outputs (shown in Figure 7). These outputs
are ideal to replace functions often provided by DIP switches. In
addition, they can be used to drive other standard CMOS logic
controlled parts that need an occasional setting change.
Figure 7.Logic Outputs O1 and O2
