AD5220BR10-AD5220BRM10-AD5220BRM50 Fast Delivery |IC PHOENIX CO.,LIMITED

AD5220BR10 ,Increment/Decrement Digital PotentiometerCHARACTERISTICS Applies to All PartsInput Clock Pulsewidth t , t Clock Level High or Low 25 nsCH CL ..
AD5220BRM10 ,Increment/Decrement Digital Potentiometerapplications. A choice betweenbandwidth or power dissipation are available as a result of thewide s ..
AD5220BRM100-REEL7 , Increment/Decrement Digital Potentiometer
AD5220BRM50 ,Increment/Decrement Digital PotentiometerSpecifications subject to change without notice.–2– REV. 0AD5220ABSOLUTE MAXIMUM RATINGS*PIN CONFIG ..
AD5220BRM50 ,Increment/Decrement Digital PotentiometerSpecifications Apply to All VRsResolution N 7 Bits3Integral Nonlinearity INL R = 10 kW –1 – 0.5 +1 ..
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AD8842AN ,8-Bit Octal, 4-Quadrant Multiplying, CMOS TrimDACSPECIFICATIONSInput Clock Pulse Width t , t 60 nsCH CL40 nsData Setup Time tDSData Hold Time t 20 n ..
AD8842AR ,8-Bit Octal, 4-Quadrant Multiplying, CMOS TrimDACSPECIFICATIONS(V = +5 V, V = –5 V, All V x = +3 V, T = –40°C to +85°C, unless otherwise noted.)ELEC ..

AD5220BR10-AD5220BRM10-AD5220BRM50
Increment/Decrement Digital Potentiometer
REV.0
Increment/Decrement
Digital Potentiometer
FUNCTIONAL BLOCK DIAGRAM
VDD
GND
CLK
U/D
FEATURES
128 Position
Potentiometer Replacement
10 kV, 50 kV, 100 kV
Very Low Power: 40 mA Max
Increment/Decrement Count Control
APPLICATIONS
Mechanical Potentiometer Replacement
Remote Incremental Adjustment Applications
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Power Supply Adjustment
GENERAL DESCRIPTION
The AD5220 provides a single channel, 128-position digitally
controlled variable resistor (VR) device. This device performs
the same electronic adjustment function as a potentiometer or
variable resistor. These products were optimized for instrument
and test equipment push-button applications. A choice between
bandwidth or power dissipation are available as a result of the
wide selection of end-to-end terminal resistance values.
The AD5220 contains a fixed resistor with a wiper contact that
taps the fixed resistor value at a point determined by a digitally
controlled UP/DOWN counter. The resistance between the
wiper and either end point of the fixed resistor provides a con-
stant resistance step size that is equal to the end-to-end resis-
tance divided by the number of positions (e.g., RSTEP = 10 kW/
128 = 78 W). The variable resistor offers a true adjustable value
of resistance, between the A terminal and the wiper, or the B
terminal and the wiper. The fixed A-to-B terminal resistance of
10 kW, 50 kW, or 100 kW has a nominal temperature coefficient
of 800 ppm/°C.
The chip select CS, count CLK and U/D direction control
inputs set the variable resistor position. These inputs that con-
trol the internal UP/DOWN counter can be easily generated
with mechanical or push button switches (or other contact closure
devices). External debounce circuitry is required for the nega-
tive-edge sensitive CLK pin. This simple digital interface elimi-
nates the need for microcontrollers in front panel interface designs.
The AD5220 is available in both surface mount (SO-8) and the
8-lead plastic DIP package. For ultracompact solutions selected
models are available in the thin mSOIC package. All parts are
guaranteed to operate over the extended industrial temperature
range of –40°C to +85°C. For 3-wire, SPI compatible inter-
face applications, see the AD7376/AD8400/AD8402/AD8403
products.
UPCOUNT DETAIL
VDD = 5.5V
VA = 5.5V
VB = 0V
f = 100kHz
CLK
VWB
50mV/DIV
5V/DIV
Figure 2a.Stair-Step Increment Output

VDD = 5.5V
VA = 5.5V
VB = 0V
f = 60kHz
COUNT
00H v 3FH v 00H
VWR
fCLK = 60kHz
Figure 2b.Full-Scale Up/Down Count
INCREMENT
Figure 1.Typical Push-Button Control Application
AD5220–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
NOTESTypicals represent average readings at +25°C and VDD = +5 V.Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 29 test circuit.INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of –1 LSB maximum are guaranteed monotonic operating conditions. See Figure 28 test circuit.Resistor terminals A, B, W have no limitations on polarity with respect to each other.Guaranteed by design and not subject to production test.PDISS is calculated from (IDD · VDD). CMOS logic level inputs result in minimum power dissipation.Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band-
width. The highest R value results in the minimum overall power consumption.All dynamic characteristics use VDD = +5 V.See timing diagrams for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level
(VDD = +3 V 6 10% or +5 V 6 10%, VA = +VDD, VB = 0 V, –408C < TA < +858C unless
otherwise noted)
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +7 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . .0 V, VDD
AX–BX, AX–WX, BX–WX . . . . . . . . . . . . . . . . . . . . . .–20 mA
Digital Input Voltage to GND . . . . . . . . . . .0 V, VDD + 0.3 V
Operating Temperature Range . . . . . . . . . . .–40°C to +85°C
Maximum Junction Temperature (TJ MAX) . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
Package Power Dissipation . . . . . . . . . . . . . .(TJ max–TA)/qJA
Thermal Resistance qJA
P-DIP (N-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . .103°C/W
SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . .158°C/WSOIC (RM-8) . . . . . . . . . . . . . . . . . . . . . . . . . . .206°C/W
*Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
PIN CONFIGURATION
tCSStCH
tUDS
CLK
U/D
Figure 3.Detail Timing Diagram
ORDERING GUIDE
NOTE
The AD5220 die size is 37 mil · 54 mil, 1998 sq mil; 0.938 mm · 1.372 mm, 1.289 sq mm. Contains 754 transistors. Patent Number 5495245 applies.
Table I.Truth Table
PIN FUNCTION DESCRIPTIONS
AD5220
–Typical Performance Characteristics
PERCENT OF NOMINAL
END-TO-END RESISTANCE – % R
CODE – Decimal
Figure 4.Wiper to End Terminal
Resistance vs. Code
CODE – Decimal
RDNL – LSB
–0.3
Figure 7.R-DNL Relative Resistance
Step Position Nonlinearity Error vs.
Code
CODE – Decimal
DNL – LSB
–0.3
Figure 10.Potentiometer Divider
DNL Error vs. Code
CONDUCTION CURRENT, IWB – mA
– V020120406080100
Figure 5.Resistance Linearity vs.
Conduction Current
CODE – Decimal
RINL – LSB
–0.3
Figure 8.R-INL Resistance Non-
linearity Error vs. Supply Voltage
SUPPLY VOLTAGE – V
POTENTIOMETER DIVIDER
NONLINEARITY – LSB
0.375
Figure 11.Potentiometer Divider
INL Error vs. Supply Voltage

WIPER RESISTANCE – V
FREQUENCY36445260
Figure 6.Wiper Contact Resistance
CODE – Decimal
INL – LSB
–0.3
Figure 9.Potentiometer Divider INL
Error vs. Code

TEMPERATURE – 8C
NOMINAL END-TO-END RESISTANCE – k100–40–1585103560
Figure 12.Nominal Resistance vs.
Temperature
CODE – Decimal
POTENTIOMETER MODE TEMPCO – ppm/60
–100161283248648096112
Figure 13.DVWB/DT Potentiometer
Mode Tempco (10 kW and 50 kW)
FREQUENCY – Hz
GAIN – dB1M10k100k
–54
Figure 16.50 kW Gain vs. Frequency
vs. Code
VWB
VDD = +5.5V
VA = +5.5V
VB = 0V
f = 100kHz
DATA
40H v 3FH
150mV
100mV
50mV
0mVCLK
TIME 500ns / DIV
Figure 19.Midscale Transition Glitch
CODE – Decimal
RHEOSTAT MODE TEMPCO – ppm/
–100161283248648096112
Figure 14.DRWB/DT Rheostat
FREQUENCY – Hz
GAIN – dB1M10k100k
–54
Figure 17.100 kW Gain vs. Fre-
quency vs. Code
FREQUENCY – Hz
THD + NOISE – %
1001k10k100k
Figure 20. Total Harmonic Distortion
Plus Noise vs. Frequency
FREQUENCY – Hz
GAIN – dB1M10k100k
–54
Figure 15.10 kW Gain vs. Frequency
vs. Code
VWB
VDD = +5.5V
VA = VB = 0V
f = 100kHz
20mV/
DIV
TIME 2ms / DIV
Figure 18.Digital Feedthrough
FREQUENCY – Hz
NORMALIZED GAIN FLATNESS – dB
–6.81001M
–6.310k100k
–6.7
Figure 21.Normalized Gain Flatness
vs. Frequency
AD5220
100k1k10k
FREQUENCY – Hz
PSRR – dB
Figure 22.Power Supply Rejection
vs. Frequency
TEMPERATURE – 8C
SUPPLY CURRENT – mA
0.01
Figure 25.Supply Current vs. Tem-
perature IDD
CLOCK FREQUENCY – Hz
– SUPPLY CURRENT –
40010M
10k100k1M
250
Figure 23.IDD Supply Current vs.
Clock Frequency
DIGITAL INPUT VOLTAGE – V
SUPPLY CURRENT – mA
1.02.03.04.05.0
Figure 26.Supply Current vs. Input
Logic Voltage
VB – Volts
– 0162345
Figure 24.Incremental Wiper
Contact Resistance vs. VB

Partno	Mfg	Dc	Qty	Available	Descript
AD5220BR10	AD	N/a	650	avai	Increment/Decrement Digital Potentiometer
AD5220BRM10	AD	N/a	8	avai	Increment/Decrement Digital Potentiometer
AD5220BRM50	ADI	N/a	480	avai	Increment/Decrement Digital Potentiometer
AD5220BRM50	ANALOG	N/a	303	avai	Increment/Decrement Digital Potentiometer