AD5207 ,Dual, 256 Position, Digital PotentiometerSpecifications Apply to All VRsResolution N 8 Bits4Integral Nonlinearity INL –1.5 +1.5 LSB4Differen ..
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AD5207
Dual, 256 Position, Digital Potentiometer
REV.0
2-Channel, 256-Position
Digital Potentiometer
FUNCTIONAL BLOCK DIAGRAM
FEATURES
256-Position, 2-Channel
Potentiometer Replacement
10 k�, 50 k�, 100 k�
Power Shut-Down, Less than 5 �A
2.7 V to 5.5 V Single Supply�2.7 V Dual Supply
3-Wire SPI-Compatible Serial Data Input
Midscale Preset During Power-On
APPLICATIONS
Mechanical Potentiometer Replacement
Stereo Channel Audio Level Control
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Automotive Electronics Adjustment
GENERAL DESCRIPTIONThe AD5207 provides dual channel, 256-position, digitally
controlled variable resistor (VR) devices that perform the same
electronic adjustment function as a potentiometer or variable
resistor. Each channel of the AD5207 contains a fixed resistor with
a wiper contact that taps the fixed resistor value at a point
determined by a digital code loaded into the SPI-compatible
serial-input register. The resistance between the wiper and either
end point of the fixed resistor varies linearly with respect to the
digital code transferred into the VR latch. The variable resistor
offers a completely programmable value of resistance, between
the A Terminal and the wiper or the B Terminal and the wiper.
The fixed A-to-B terminal resistance of 10 kΩ, 50 kΩ or 100 kΩ
has a ±1% channel-to-channel matching tolerance with a nomi-
nal temperature coefficient of 500 ppm/°C. A unique switching
circuit minimizes the high glitch inherent in traditional switched
resistor designs and avoids any make-before-break or break-
before-make operation.
Each VR has its own VR latch, which holds its programmed
resistance value. These VR latches are updated from an internal
serial-to-parallel shift register, which is loaded from a standard
3-wire serial-input digital interface. Ten bits, to make up the
data word, are required and clocked into the serial input register.
The first two bits are address bits. The following eight bits are
the data bits that represent the 256 steps of the resistance value.
The reason for two address bits instead of one is to be compatible
with similar products such as AD8402 so that drop-in replacement
is possible. The address bit determines the corresponding VR
latch to be loaded with the data bits during the returned positive
edge of CS strobe. A serial data output pin at the opposite end
of the serial register allows simple daisy chaining in multiple
VR applications without additional external decoding logic.
An internal reset block will force the wiper to the midscale posi-
tion during every power-up condition. The SHDN pin forces an
open circuit on the A Terminal and at the same time shorts the
wiper to the B Terminal, achieving a microwatt power shutdown
state. When SHDN is returned to logic high, the previous latch
settings put the wiper in the same resistance setting prior to
shutdown. The digital interface remains active during shutdown;
code changes can be made to produce new wiper positions when
the device is resumed from shutdown.
The AD5207 is available in 1.1 mm thin TSSOP-14 package,
which is suitable for PCMCIA applications. All parts are guaran-
teed to operate over the extended industrial temperature range
of –40°C to +125°C.
AD5207–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS 10 k�, 50 k�, 100 k� VERSION (VDD = 5 V, VSS = 0, VA = 5 V,
VB = 0, –40�C < TA < +125�C unless otherwise noted.)
AD5207NOTESTypicals represent average readings at 25°C and VDD = 5 V, VSS = 0 V.Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD = 5 V,
VSS = 0 V.VAB = VDD, Wiper (VW) = No connect.INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL
specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions.Resistor Terminals A, B, W have no limitations on polarity with respect to each other.Guaranteed by design and not subject to production test.Measured at the AX terminals. All AX terminals are open-circuited in shut-down mode.PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.All dynamic characteristics use VDD = 5 V, VSS = 0 V.Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of
1.5 V. Switching characteristics are measured using VDD = 5 V.Propagation delay depends on value of VDD, RL, and CL; see applications text.
The AD5207 contains 474 transistors. Die Size: 67 mil × 69 mil, 4623 sq. mil.
Specifications subject to change without notice.
Figure 1a.Timing Diagram
AD5207
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5207 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
ABSOLUTE MAXIMUM RATINGS1(TA = 25°C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0, –3 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
IMAX2 (A, B, W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Digital Inputs and Output Voltage to GND . . 0 V, VDD + 0.3 V
Operating Temperature Range . . . . . . . . . . –40°C to +125°C
Maximum Junction Temperature (TJ Max) . . . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Thermal Resistance3 θJA, TSSOP-14 . . . . . . . . . . . . . 206°C/W
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Max current is bounded by the maximum current handling of the switches,
maximum power dissipation of the package, and maximum applied voltage
across any two of the A, B, and W Terminals at a given resistance. Please refer to
TPC22 for detail.Package Power Dissipation = (TJ Max–TA)/θJA.
PIN FUNCTION DESCRIPTIONS
Table I.Serial-Data Word FormatNOTES
ADDR(RDAC1) = 00; ADDR(RDAC2 = 01).
Data loads B9 first into SDI pin.
PIN CONFIGURATION
ORDERING GUIDE*Three lines of information appear on the device. Line 1 lists the part number; Line 2 includes branding information and the ADI logo, and Line 3 contains the
date code YYWW.
CODE – Decimal�0.20
RDNL – LSB
224�0.15
�0.10
�0.05
1921601289664320256TPC 1.10 kΩ RDNL vs. Code
CODE – Decimal
RINL
LSB
0.05TPC 2.10 kΩ RINL vs. Code
CODE – Decimal
DNL
LSB
0.2TPC 3.10 kΩ DNL vs. Code
TPC 4.10 kΩ INL vs. Code
TPC 5.Supply Current vs. Logic Input Voltage
TPC 6.Supply Current vs. Temperature
AD5207TPC 7.Shutdown Current vs. Temperature
VSUPPLY – V
ON
1004321TPC 8.Wiper ON Resistance vs. VSUPPLY
TPC 9.10 kΩ Supply Current vs. Clock Frequency
TPC 10.10 kΩ Supply Current vs. Clock Frequency
TPC 11.Power Supply Rejection Ratio vs. Frequency
TPC 12.10 kΩ Gain vs. Frequency vs. Code
TPC 13.50 kΩ Gain vs. Frequency vs. Code
TPC 14.100 kΩ Gain vs. Frequency vs. Code
TPC 15.–3 dB Bandwidth
TPC 16.Normalized Gain Flatness vs. Frequency
(10mV/DIV)TPC 17.One Position Step Change at Half Scale
OUT
(50mV/DIV)
(5mV/DIV)TPC 18.Large Signal Settling Time
AD5207
(10mV/DIV)TPC 19.Digital Feedthrough vs. Time
CODE – Decimal
120�40
TENTIOMETER MODE TEMPCO
ppm/
–206496128160192224256TPC 20.∆VWB/∆T Potentiometer Mode
Temperature Coefficient
CODE – Decimal�500
RHEOST
T MODE
TEMPCO
ppm/
5006496128160192224256TPC 21.∆RWB/∆T Rheostat Mode Temperature Coefficient
TPC 22.IMAX vs. Code
