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AD5203
4-Channel, 64-Position Digital Potentiometer
REV.0
4-Channel, 64-Position
Digital Potentiometer
FUNCTIONAL BLOCK DIAGRAM
FEATURES
64 Position
Replaces Four Potentiometers
10 kV, 100 kV
Power Shutdown—Less than 5 mA
3-Wire SPI-Compatible Serial Data Input
10 MHz Update Data Loading Rate
+2.7 V to +5.5 V Single Supply Operation
Midscale Preset
APPLICATIONS
Mechanical Potentiometer Replacement
Programmable Filters, Delays, Time Constants
Volume Control, Panning
Line Impedance Matching
Power Supply Adjustment
GENERAL DESCRIPTIONThe AD5203 provides a quad channel, 64-position digitally-
controlled variable resistor (VR) device. These parts perform the
same electronic adjustment function as a potentiometer or vari-
able resistor. The AD5203 contains four independent variable
resistors in a 24-lead SOIC and the compact TSSOP-24 pack-
ages. Each part contains a fixed resistor with a wiper contact
that taps the fixed resistor value at a point determined by a digi-
tal code loaded into the controlling serial input register. The
resistance between the wiper and either endpoint of the fixed
resistor varies linearly with respect to the digital code transferred
into the VR latch. Each variable resistor offers a completely
programmable value of resistance, between the A terminal and
the wiper or the B terminal and the wiper. The fixed A-to-B
terminal resistance of 10 kW, or 100 kW has a –1% channel-to-
channel matching tolerance with a nominal temperature coeffi-
cient of 700 ppm/°C.
Each VR has its own VR latch which holds its programmed
resistance value. These VR latches are updated from an internal
serial-to-parallel shift register that is loaded from a standard
3-wire serial-input digital interface. Eight data bits make up the
data word clocked into the serial input register. The data word is
decoded where the first two bits determine the address of the VR
latch to be loaded, the last 6-bits are data. A serial data output
pin at the opposite end of the serial register allows simple daisy-
chaining in multiple VR applications without additional external
decoding logic.
The reset RS pin forces the wiper to the midscale position by
loading 20H into the VR latch. The SHDN pin forces the resis-
tor to an end-to-end open circuit condition on terminal A and
shorts the wiper to terminal B, achieving a microwatt power
shutdown state. When shutdown is returned to logic-high the
previous latch settings put the wiper in the same resistance set-
ting prior to shutdown.
The AD5203 is available in a narrow body P-DIP-24, the
24-lead surface mount package, and the compact 1.1 mm thin
TSSOP-24 package. All parts are guaranteed to operate over the
extended industrial temperature range of –40°C to +85°C.
For pin compatible higher resolution applications, see the 256-
position AD8403 product.
AD5203–SPECIFICATIONS
ELECTRICAL CHARACTERISTICSDC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs
(VDD = +3 V 6 10% or +5 V 6 10%, VA = +VDD, VB = 0 V, –408C < TA < +858C unless
otherwise noted)
AD5203NOTESTypicals represent average readings at +25°C and VDD = +5 V.Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27 test circuit. IW = VDD/R
for both VDD = +3 V or VDD = +5 V.VAB = VDD, Wiper (VW) = No connect.INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of –1 LSB maximum are guaranteed monotonic operating conditions. See Figure 26 test circuit.Resistor terminals A, B, W have no limitations on polarity with respect to each other.Guaranteed by design and not subject to production test.Measured at the AX terminals. All AX terminals are open-circuited in shutdown mode.Worst case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic. See Figure 19 for a plot of IDD vs. logic voltage
inputs result in minimum power dissipation.PDISS is calculated from (IDD · VDD). CMOS logic level inputs result in minimum power dissipation.All dynamic characteristics use VDD = +5 V.Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.See timing diagrams for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both VDD = +3 V or +5 V. Input logic should have a 1 V/ms minimum slew rate.Propagation delay depends on value of VDD, RL and CL. See Operation section.
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +8 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . .0 V, VDD
IAB, IAW, IBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–20 mA
Digital Input and Output Voltage to GND . . . . . . .0 V, +8 V
Operating Temperature Range . . . . . . . . . . .–40°C to +85°C
Maximum Junction Temperature (TJ MAX) . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
Package Power Dissipation . . . . . . . . . . . . . .(TJ max–TA)/qJA
Thermal Resistance qJA
P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . .63°C/W
SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . .70°C/W
TSSOP-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143°C/W
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Table I.Serial-Data Word Format
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5203 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
Figure 1a.Timing Diagram
Figure 1b.Detail Timing Diagram
Figure 1c.Reset Timing Diagram
AD5203
PIN FUNCTION DESCRIPTIONS*All AGNDs must be connected to DGND voltage potential.
ORDERING GUIDE
PIN CONFIGURATION
SDI
SHDN
DGND
AGND2
AGND4
SDO
CLK
VDD
AGND3
AGND1
CODE – Decimal
RESISTANCE – k64162432404856 Figure 2.Wiper to End Terminal␣ Resistance vs. Code
WIPER RESISTANCE – V
FREQUENCY313233343536373839Figure 5.␣ Wiper-Contact-Resistance
Histogram
DIGITAL INPUT CODE – Decimal
DNL ERROR – LSB
–0.15Figure 8.Potentiometer Divider
Differential Nonlinearity Error vs.
Code
IWA CURRENT – mA
VOLTAGE – V01723456
2.5 Figure 3.Resistance Linearity vs.␣ Conduction Current
TEMPERATURE – 8C
NOMINAL RESISTANCE – k
–75–50125–250255075100␣ Figure 6.␣Nominal Resistance vs.␣ Temperature
CODE – Decimal
POTENTIOMETER MODE TEMPCO – ppm/5064162432404856 Figure 9.␣DVWB/DT Potentiometer
Mode Tempco
Figure 4.Resistance Step Position␣ Nonlinearity Error vs. Code
␣␣␣ Figure 7.Potentiometer Divider␣ Nonlinearity Error vs. Code
Figure 10.DRWB/DT Rheostat Mode
Tempco
AD5203
–Typical Performance Characteristics Figure 11.One Position Step Change
at Half-Scale (Code 1FH to 20H)
Figure 14.Large Signal Settling Time
–501001M1k10k100k
GAIN – dB
FREQUENCY – HzFigure 17.100 kW Gain vs. Frequency
vs. Code
–50101001M1k10k100k
10M
GAIN – dB
FREQUENCY – HzFigure 12.Gain vs. Frequency for
R = 10 kW
Figure 15.␣Total Harmonic Distortion
Plus Noise vs. Frequency
–0.51001M1k10k100k
NORMALIZED GAIN FLATNESS – 0.1dB/DIV
FREQUENCY – Hz
–1.0Figure 18.Normalized Gain Flat-
ness vs. Frequency
␣␣␣␣ Figure 13. Long-Term Drift
Accelerated by Burn-In
Figure 16.Digital Feedthrough vs.
Time
INPUT LOGIC VOLTAGE – Volts
IDD
SUPPLY CURRENT – mA
0.01Figure 19.Supply Current vs. Logic
Input Voltage
