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AD5172BRM100-AD5173BRM50
256-Position One-Time Programmable Dual-Channel I2C Digital Potentiometers
256-Position One-Time Programmable
Dual-Channel I2C Digital Potentiometers
Rev. A
FEATURES
2-channel, 256-position
OTP (one-time programmable) set-and-forget resistance
setting, low cost alternative to EEMEM
Unlimited adjustments prior to OTP activation
OTP overwrite allows dynamic adjustments with user
defined preset
End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact MSOP-10 (3 mm × 4.9 mm) package
Fast settling time: tS = 5 µs typ in power-up
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pins AD0 and AD1 (AD5173)
Single supply 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/°C
Low power, IDD = 6 µA max
Wide operating temperature: –40°C to +125°C
Evaluation board and software are available
Software replaces µC in factory programming applications
APPLICATIONS
Systems calibration
Electronics level setting
Mechanical Trimmers® replacement in new designs
Permanent factory PCB setting
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
GENERAL OVERVIEW The AD5172/AD5173 are dual channel, 256-position, one-time
programmable (OTP) digital potentiometers1 that employ fuse
link technology to achieve memory retention of resistance
setting. OTP is a cost-effective alternative to EEMEM for users
who do not need to program the digital potentiometer setting in
memory more than once. This device performs the same elec-
tronic adjustment function as mechanical potentiometers or
variable resistors with enhanced resolution, solid-state reliabil-
ity, and superior low temperature coefficient performance.
The AD5172/AD5173 are programmed using a 2-wire, I2C
compatible digital interface. Unlimited adjustments are allowed
before permanently setting the resistance value. During OTP
activation, a permanent blow fuse command freezes the wiper
position (analogous to placing epoxy on a mechanical trimmer).
FUNCTIONAL BLOCK DIAGRAMS
VDD
SDA
SCL04103-0-001
A2W2Figure 1. AD5172
VDD
SDA
SCL
AD0
AD1W204103-0-002
Figure 2. AD5173
Unlike traditional OTP digital potentiometers, the AD5172/
AD5173 have a unique temporary OTP overwrite feature that
allows for new adjustments even after the fuse has been blown.
However, the OTP setting is restored during subsequent power-
up conditions. This feature allows users to treat these digital
potentiometers as volatile potentiometers with a programmable
preset.
For applications that program the AD5172/AD5173 at the
factory, Analog Devices offers device programming software
running on Windows® NT®, 2000, and XP® operating systems.
This software effectively replaces any external I2C controllers,
thus enhancing the time-to-market of the user’s systems.
1The terms digital potentiometer, VR, and RDAC are used interchangeably.
TABLE OF CONTENTS Electrical Characteristics—2.5 kΩ.................................................3
Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions.......4
Timing Characteristics—2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions
.............................................................................................................5
Absolute Maximum Ratings............................................................6
Typical Performance Characteristics.............................................7
Test Circuits.....................................................................................11
Operation.........................................................................................12
One-Time Programming (OTP)..............................................12
Programming the Variable Resistor and Voltage....................12
Programming the Potentiometer Divider...............................13
ESD Protection...........................................................................14
Terminal Voltage Operating Range..........................................14
Power-Up Sequence...................................................................14
Power Supply Considerations...................................................14
Layout Considerations...............................................................15
Evaluation Software/Hardware.....................................................16
Software Programming.............................................................16 2C Interface....................................................................................18 2C Compatible 2-Wire Serial Bus...........................................20
Pin Configuration and Function Descriptions...........................22
Outline Dimensions.......................................................................23
Ordering Guide...............................................................................24
REVISION HISTORY Revision A
11/03—Data Sheet Changed from Rev. 0 to Rev. A
Change Location Changes to Electrical Characteristics—2.5 kΩ.........................3
ELECTRICAL CHARACTERISTICS—2.5 kΩ
Table 1. VDD = 5 V ± 10% or 3 V ± 10%; VA = +VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, Wiper (VW) = no connect. INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL
specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test. Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS
Table 2. VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted 1 Typical specifications represent average readings at 25°C and VDD = 5 V. Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. VAB = VDD, Wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor terminals A, B, W have no limitations on polarity with respect to each other. Guaranteed by design and not subject to production test.
7 Measured at the A terminal. The A terminal is open circuited in shutdown mode. Different from operating power supply, power supply OTP is used one time only.
9 Different from operating current, supply current for OTP lasts approximately 400 ms for one time only. PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
11 All dynamic characteristics use VDD = 5 V.
TIMING CHARACTERISTICS—2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS
Table 3. VDD = 5 V ± 10% or 3V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted See timing diagrams for locations of measured values.
2 The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
ABSOLUTE MAXIMUM RATINGS
Table 4. TA = 25°C, unless otherwise noted Maximum terminal current is bound by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Package power dissipation = (TJMAX – TA)/θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
TYPICAL PERFORMANCE CHARACTERISTICS
RHEOSTAT MODE INL (LSB)
CODE (DECIMAL)Figure 3. R-INL vs. Code vs. Supply Voltages
RHE
TAT MODE
DNL (LS
CODE (DECIMAL)Figure 4. R-DNL vs. Code vs. Supply Voltages
NTIOME
R MODE
INL (LS
CODE (DECIMAL)Figure 5. INL vs. Code vs. Temperature
NTIOME
R MODE
DNL (LS
CODE (DECIMAL)Figure 6. DNL vs. Code vs. Temperature
NTIOME
R MODE
INL (LS
CODE (DECIMAL)Figure 7. INL vs. Code vs. Supply Voltages
NTIOME
R MODE
DNL (LS
CODE (DECIMAL)Figure 8. DNL vs. Code vs. Supply Voltages
RHEOSTAT MODE INL (LSB)
CODE (DECIMAL)Figure 9. R-INL vs. Code vs. Temperature
RHE
TAT MODE
DNL (LS
CODE (DECIMAL)Figure 10. R-DNL vs. Code vs. Temperature
FSE, FU
LL-
E ER
TEMPERATURE (°C)
–40–25–105203550658095110125Figure 11. Full-Scale Error vs. Temperature
, ZE
RO-S
CALE
RROR (LS
TEMPERATURE (°C)
–40–25–105203550658095110125Figure 12. Zero-Scale Error vs. Temperature
IDD
, S
CURRE
NT (
TEMPERATURE (°C)Figure 13. Supply Current vs. Temperature
RHEOSTAT MODE TE
CO (ppm/°C)
CODE (DECIMAL)Figure 14. Rheostat Mode Tempco ∆RWB/∆T vs. Code
NTIOME
R MODE
TE
CO (ppm/
CODE (DECIMAL)Figure 15. AD5172 Potentiometer Mode Tempco ∆VWB/∆T vs. Code
GAIN (
FREQUENCY (Hz)
10k1M100k10MFigure 16. Gain vs. Frequency vs. Code, RAB = 2.5 kΩ
GAIN (
FREQUENCY (Hz)100k10k1MFigure 17. Gain vs. Frequency vs. Code, RAB = 10 kΩ
GAIN (
FREQUENCY (Hz)100k10k1MFigure 18. Gain vs. Frequency vs. Code, RAB = 50 kΩ
GAIN (
FREQUENCY (Hz)100k10k1MFigure 19. Gain vs. Frequency vs. Code, RAB = 100 kΩ
GAIN (
FREQUENCY (Hz)
10k1k100k1M10MFigure 20. –3 dB Bandwidth @ Code = 0x80
IDD
, S
CURRE
NT (mA)
DIGITAL INPUT VOLTAGE (V)Figure 21. IDD vs. Input Voltage
SCL
Figure 22. Digital Feedthrough
VW1
VW2
Figure 23. Digital Crosstalk
VW1
VW2
Figure 24. Analog Crosstalk
Figure 25. Midscale Glitch, Code 0x80 to 0x7F
SCL
Figure 26. Large Signal Settling Time
TEST CIRCUITS Figure 27 to Figure 34 illustrate the test circuits that define the
test conditions used in the product specification tables.
04103-0-015
W= VDD
1LSB = V+/2NFigure 27. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
NO CONNECT
Figure 28. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
VMS2= [VMS1– VMS2]/IW
Figure 29. Test Circuit for Wiper Resistance
∆VMS%
DD%PSS (%/%) = = VDD10%
PSRR (dB) = 20 LOGMS( )∆V
Figure 30. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
2.5VOFFSETGND
DUT
VIN
Figure 31. Test Circuit for Gain vs. Frequency
RSW=0.1V
0.1V
GND TO VDD
Figure 32. Test Circuit for Incremental On Resistance
04103-0-021
Figure 33. Test Circuit for Common-Mode Leakage Current
VIN
VOUT
CTA = 20 log[VOUT/VIN]
Figure 34. Test Circuit for Analog Crosstalk
OPERATION
SDA
SCL04103-0-026
Figure 35. Detailed Functional Block Diagram
The AD5172/AD5173 is a 256-position, digitally controlled
variable resistor (VR) that employs fuse link technology to
achieve memory retention of resistance setting.
An internal power-on preset places the wiper at midscale
during power-on. If the OTP function has been activated, the
device powers up at the user-defined permanent setting.
ONE-TIME PROGRAMMING (OTP) Prior to OTP activation, the AD5172/AD5173 presets to mid-
scale during initial power-on. After the wiper is set at the
desired position, the resistance can be permanently set by
programming the T bit high along with the proper coding (see
Table 5 and Table 6). Note that fuse link technology requires 6 V
to blow the internal fuses to achieve a given setting. The user is
allowed only one attempt at blowing the fuses. Once program-
ming is completed, the power supply voltage must be reduced to
the normal operating range of 2.7 V to 5.5 V.
The device control circuit has two validation bits, E1 and E0,
that can be read back to check the programming status (see
Table 7). Users should always read back the validation bits to
ensure that the fuses are properly blown. After the fuses have
been blown, all fuse latches are enabled upon subsequent
power-on; therefore, the output corresponds to the stored
setting. Figure 35 shows a detailed functional block diagram.
PROGRAMMING THE VARIABLE RESISTOR AND
VOLTAGE
Rheostat Operation The nominal resistance of the RDAC between terminals A and
B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The nominal
resistance (RAB) of the VR has 256 contact points accessed by
the wiper terminal, plus the B terminal contact. The 8-bit data
04103-0-027
Figure 36. Rheostat Mode Configuration
Assuming a 10 kΩ part is used, the wiper’s first connection
starts at the B terminal for data 0x00. Because there is a 50 Ω
wiper contact resistance, such a connection yields a minimum
of 100 Ω (2 × 50 Ω) resistance between terminals W and B. The
second connection is the first tap point, which corresponds to
139 Ω (RWB = RAB/256 + 2 × RW = 39 Ω + 2 × 50 Ω) for data
0x01. The third connection is the next tap point, representing
178 Ω (2 × 39 Ω + 2 × 50 Ω) for data 0x02, and so on. Each LSB
data value increase moves the wiper up the resistor ladder until
the last tap point is reached at 10,100 Ω (RAB + 2 × RW).
04103-0-028
