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AD5165BUJZ100-R2-AD5165BUJZ100-R7
256-Position, Ultralow Power 1.8 V Logic-Level Digital Potentiometer
256-Position, Ultralow Power
1.8 V Logic-Level Digital Potentiometer
Rev. 0
FEATURES
Ultralow standby power IDD = 50 nA typical
256-position
End-to-end resistance 100 kΩ
Logic high voltage 1.8 V
Power supply 2.7 V to 5.5 V
Low temperature coefficient 35 ppm/°C
Compact thin 8-lead TSOT-8 (2.9 mm × 2.8 mm) package
Simple 3-wire digital interface
Wide operating temperature −40°C to +125°C
Pin-to-pin compatible to AD5160 with CS inverted
APPLICATIONS
Battery-operated electronics adjustment
Remote utilities meter adjustment
Mechanical potentiometer replacement
Transducer circuit adjustment
Automotive electronics adjustment
Gain control and offset adjustment
System calibration
VCXO adjustment
GENERAL OVERVIEW The AD5165 provides a compact 2.9 mm × 2.8 mm packaged
solution for 256-position adjustment applications. These devices
perform the same electronic adjustment function as mechanical
potentiometers or variable resistors, with enhanced resolution,
solid-state reliability, and superior low temperature coefficient
performance. The AD5165’s supply voltage requirement is 2.7 V
to 5.5 V, but its logic voltage requirement is 1.8 V to VDD. The
AD5165 consumes very low quiescent power during standby
mode and is ideal for battery-operated applications.
Wiper settings are controlled through a simple 3-wire interface.
The interface is similar to the SPI® digital interface except for the
inverted chip-select function that minimizes logic power con-
sumption in the idling state. The resistance between the wiper
and either endpoint of the fixed resistor varies linearly with
respect to the digital code transferred into the wiper register.
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 50 nA typical standby power allows use in battery-
operated portable or remote utility device applications.
FUNCTIONAL BLOCK DIAGRAM
CS
SDI
CLK
GND
VDDFigure 1.
PIN CONFIGURATION
SDI
VDD
GND
CLK04749-0-002
Figure 2.
TYPICAL APPLICATION WIDE TERMINAL
VOLTAGE RANGE:
0V < VA,VB,VW< 5V
Figure 3.
Note:
The terms digital potentiometer, RDAC, and VR are used interchangeably.
TABLE OF CONTENTS Electrical Characteristics—100 kΩ Version..................................3
Absolute Maximum Ratings............................................................5
Pin Configuration and Functional Descriptions..........................6
Typical Performance Characteristics.............................................7
Test Circuits.....................................................................................11
3-Wire Digital Interface.................................................................12
Theory of Operation......................................................................13
Programming the Variable Resistor.........................................13
Programming the Potentiometer Divider...............................14
3-Wire Serial Bus Digital Interface..........................................14
ESD Protection...........................................................................14
Terminal Voltage Operating Range..........................................14
Power-Up Sequence...................................................................14
Layout and Power Supply Bypassing.......................................15
Evaluation Board........................................................................15
Outline Dimensions.......................................................................16
Ordering Guide..........................................................................16
REVISION HISTORY
4/04—Revision 0: Initial Version
ELECTRICAL CHARACTERISTICS—100 kΩ VERSION VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.
Table 1. 1 Typical specifications represent average readings at +25°C and VDD = 5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. Resistor terminals A, B, and W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test. PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 All dynamic characteristics use VDD = 5 V.
TIMING CHARACTERISTICS—100 kΩ VERSION VDD = +5 V ± 10%, or +3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 2. Typical specifications represent average readings at +25°C and VDD = 5 V.
2 Guaranteed by design and not subject to production test. All dynamic characteristics use VDD = 5 V.
4 See and for location of measured values. All input control voltages are specified with tFigure 34Figure 35R = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V.
ABSOLUTE MAXIMUM RATINGS TA = +25°C, unless otherwise noted.1, 2
Table 3. Maximum terminal current is bounded by the maximum current handling
of the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Package power dissipation = (TJMAX − TA)/θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
SDI
VDD
GND
CLK04749-0-002
Figure 4.
Table 4. TYPICAL PERFORMANCE CHARACTERISTICS
RHEOSTAT MODE INL (LSB)
CODE (Decimal)Figure 5. R-INL vs. Code vs. Supply Voltages
HOS
AT MODE
DNL (LS
CODE (Decimal)Figure 6. R-DNL vs. Code vs. Supply Voltages
NTIOME
R MODE
INL (LS
CODE (Decimal)Figure 7. INL vs. Code vs. Temperature , VDD = 5 V
NTIOME
R MODE
DNL (LS
CODE (Decimal)Figure 8. DNL vs. Code vs. Temperature, VDD = 5 V
NTIOME
R MODE
INL (LS
CODE (Decimal)Figure 9. INL vs. Code vs. Supply Voltages
NTIOME
R MODE
DNL (LS
CODE (Decimal)Figure 10. DNL vs. Code vs. Supply Voltages
RHEOSTAT MODE INL (LSB)
CODE (Decimal)Figure 11. R-INL vs. Code vs. Temperature, VDD = 5 V
RHE
TAT MODE
DNL (LS
CODE (Decimal)Figure 12. R-DNL vs. Code vs. Temperature, VDD = 5 V
FSE (LSB)20–200–406080100120
TEMPERATURE (°C)Figure 13. Full-Scale Error vs. Temperature
ZSE (20–200–406080100120
TEMPERATURE (°C)Figure 14. Zero-Scale Error vs. Temperature
PPLY C20–200–406080100120
TEMPERATURE (°C)Figure 15. Supply Current vs. Temperature
IDD2345
VIH (0) (V)Figure 16. Supply Current vs. Digital Input Voltage
