AD5161BRM10 Fast Delivery |IC PHOENIX CO.,LIMITED

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AD5161BRM10
256 Position SPI/I2C Selectable Digital Potentiometer
256-Position SPI/I2C Selectable
Digital Potentiometer
Rev. 0
FEATURES
256-position
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact MSOP-10 (3 mm × 4.9 mm) package
Pin selectable SPI/I2C compatible interface
Extra package address decode pin AD0
Full read/write of wiper register
Power-on preset to midscale
Single supply 2.7 V to 5.5 V
Low temperature coefficient 45 ppm/°C
Low power, IDD = 8 µA
Wide operating temperature –40°C to +125°C
SDO output allows multiple device daisy-chaining
Evaluation board available
APPLICATIONS
Mechanical potentiometer replacement in new designs
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
GENERAL OVERVIEW
The AD5161 provides a compact 3 mm × 4.9 mm packaged
solution for 256-position adjustment applications. These devices
perform the same electronic adjustment function as mechanical
potentiometers or variable resistors, with enhanced resolution,
solid-state reliability, and superior low temperature coefficient
performance.
The wiper settings are controllable through a pin selectable SPI
or I2C compatible digital interface, which can also be used to
read back the wiper register content. When the SPI mode is
used, the device can be daisy-chained (SDO to SDI), allowing
several parts to share the same control lines. In the I2C mode,
address pin AD0 can be used to place up to two devices on the
same bus. In this same mode, command bits are available to
reset the wiper position to midscale or to shut down the device
into a state of zero power consumption.
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 5 µA allows for usage in portable battery-operated
applications.
FUNCTIONAL BLOCK DIAGRAM
SDI/SDA
CLK/SCL
DIS
CS/AD0
GND
SDO/NCVDD
Figure 1.
PIN CONFIGURATION
CS/ADO
SDO/NCAD5161
TOP VIEW
(Not to Scale)
DIS
GND
CLK/SCL
Figure 2.
Note:
The terms digital potentiometer, VR, and RDAC are used interchangeably.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed
Associated Companies conveys a license for the purchaser under the Philips I2C
Patent Rights to use these components in an I2C system, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
TABLE OF CONTENTS
Electrical Characteristics—5 kΩ Version......................................3
Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions.......4
Timing Characteristics—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions5
Absolute Maximum Ratings1..........................................................6
Typical Performance Characteristics.............................................7
Test Circuits.....................................................................................11
SPI Interface....................................................................................12 2C Interface.....................................................................................13
Operation.........................................................................................14
Programming the Variable Resistor.........................................14
Programming the Potentiometer Divider...............................15
Pin Selectable Digital Interface.................................................15
Level Shifting for Bidirectional Interface................................17
ESD Protection...........................................................................17
Terminal Voltage Operating Range..........................................17
Power-Up Sequence...................................................................17
Layout and Power Supply Bypassing.......................................17
Pin Configuration and Function Descriptions...........................18
Pin Configuration......................................................................18
Pin Function Descriptions........................................................18
Outline Dimensions.......................................................................19
Ordering Guide..........................................................................19
ESD Caution................................................................................19
REVISION HISTORY
Revision 0: Initial Version
ELECTRICAL CHARACTERISTICS—5 kΩ VERSION
(VDD = 5 V ± 10%, or 3 V ± 10%; VA = +VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.)
Table 1.
ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS
(VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.)
Table 2.
TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS
(VDD = +5V ± 10%, or +3V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.)
Table 3.

NOTES
1 Typical specifications represent average readings at +25°C and VDD = 5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. VAB = VDD, Wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor terminals A, B, W have no limitations on polarity with respect to each other. Guaranteed by design and not subject to production test.
7 Measured at the A terminal. The A terminal is open circuited in shutdown mode. PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9 All dynamic characteristics use VDD = 5 V. See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V. See timing diagrams for locations of measured values.
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C, unless otherwise noted.)
Table 4
NOTES Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance. Package power dissipation = (TJMAX – TA)/θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
TYPICAL PERFORMANCE CHARACTERISTICS
CODE (Decimal)
RHEOSTAT MODE INL (LSB)
0.8
Figure 3. R-INL vs. Code vs. Supply Voltages
RHE
TAT MODE
DNL (LS
CODE (Decimal)09664128160192224256
Figure 4. R-DNL vs. Code vs. Supply Voltages
NTIOME
R MODE
INL (LS
CODE (Decimal)09664128160192224256
Figure 5. INL vs. Code, VDD = 5 V
CODE (Decimal)
NTIOME
R MODE
DNL (LS
0.8
Figure 6. DNL vs. Code, VDD = 5 V
NTIOME
R MODE
INL (LS
CODE (Decimal)09664128160192224256
Figure 7. INL vs. Code vs. Supply Voltages
CODE (Decimal)
NTIOME
R MODE
DNL(LS
1.0
Figure 8. DNL vs. Code vs. Supply Voltages
RHEOSTAT M
DE INL (LSB)
CODE (Decimal)09664128160192224256
Figure 9. R-INL vs. Code, VDD = 5 V
RHE
TAT MODE
DNL (LS
CODE (Decimal)09664128160192224256
Figure 10. R-DNL vs. Code, VDD = 5 V
TEMPERATURE (°C)4080120–40
FSE, FU
LL-
E ER4080120–40
0.5
Figure 11. Full-Scale Error vs. Temperature 4080120–400
, ZE
RO-S
CALE
RROR (
TEMPERATURE (°C)4080120–40
0.5
Figure 12. Zero-Scale Error vs. Temperature
TEMPERATURE (°C)4080120–40
CURRE
NT (
Figure 13. Supply Current vs. Temperature
HUTDOWN CURRE
NT (nA)
TEMPERATURE (°C)80120–40
Figure 14. Shutdown Current vs. Temperature
CODE (Decimal)
RHEOSTAT MODE TEMPCO
(ppm/°C)
CODE (Decimal)
NTIOME
R MODE
TE
(ppm/°C)10k100k1M
REF LEVEL
0.000dB
/DIV
6.000dB
MARKER 1 000 000.000Hz
MAG (A/R)–8.918dB
START 1 000.000Hz STOP 1 000 000.000Hz
Figure 17. Gain vs. Frequency vs. Code, RAB = 5 kΩ 10k100k1M
REF LEVEL
0.000dB
/DIV
6.000dB
MARKER 510 634.725Hz
MAG (A/R)–9.049dB
START 1 000.000Hz STOP 1 000 000.000Hz
Figure 18. Gain vs. Frequency vs. Code, RAB = 10 kΩ 10k100k1M
REF LEVEL
0.000dB
/DIV
6.000dB
MARKER 100 885.289Hz
MAG (A/R)–9.014dB
START 1 000.000Hz STOP 1 000 000.000Hz
Figure 19. Gain vs. Frequency vs. Code, RAB = 50 kΩ 10k100k1M
REF LEVEL
0.000dB
/DIV
6.000dB
MARKER 54 089.173Hz
MAG (A/R)–9.052dB
START 1 000.000Hz STOP 1 000 000.000Hz
Figure 20. Gain vs. Frequency vs. Code, RAB = 100 kΩ
10k100k1M10M
REF LEVEL
–5.000dB
/DIV
0.500dB
START 1 000.000Hz STOP 1 000 000.000Hz
Figure 21. –3 dB Bandwidth @ Code = 0x80
FREQUENCY (Hz)
10k100100k1M1k0
RR (dB)
Figure 22. PSRR vs. Frequency
IDD
FREQUENCY (Hz)
10k
100k1M10M0
Figure 23. IDD vs. Frequency
CLK
Figure 24. Digital Feedthrough
Figure 25. Midscale Glitch, Code 0x80–0x7F
Figure 26. Large Signal Settling Time, Code 0xFF–0x00

Partno	Mfg	Dc	Qty	Available	Descript
AD5161BRM10	AD	N/a	1	avai	256 Position SPI/I2C Selectable Digital Potentiometer