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AD8602A , Operational Amplifiers Selection Guide
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AD8602ARM ,Precision CMOS Single Supply Rail-to-Rail Input/Output Wideband Operational AmplifiersCHARACTERISTICSOutput Voltage High V I = 1.0 mA 2.92 2.96 2.92 2.96 VOH L–40°C ≤ T ≤ +125°C 2.88 2. ..
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AD8602ARM-REEL ,DigiTrim™ Dual Rail-to-Rail Input and Output Amplifier with Very Low Offset Voltage and Wide BandwidthsCHARACTERISTICSOffset Voltage (AD8601/AD8602) V 0 V ≤ V ≤ 5 V 80 500 1,300 6,000 µVOS CM–40°C ≤ T ≤ ..
AD420AN-32-AD420AR-32
Serial Input 16-Bit 4 mA-20 mA, 0 mA-20 mA DAC
FUNCTIONAL BLOCK DIAGRAMREV.F
Serial Input 16-Bit
4 mA–20 mA, 0 mA–20 mA DAC
FEATURES
4 mA–20 mA, 0 mA–20 mA or 0 mA–24 mA Current Output
16-Bit Resolution and Monotonicity60.012% Max Integral Nonlinearity
60.05% Max Offset (Trimmable)
60.15% Max Total Output Error (Trimmable)
Flexible Serial Digital Interface (3.3 MBPS)
On-Chip Loop Fault Detection
On-Chip 5 V Reference (25 ppm/8C Max)
Asynchronous CLEAR Function
Maximum Power Supply Range of 32 V
Output Loop Compliance of 0 V to VCC – 2.5 V
24-Lead SOIC and PDIP Packages
PRODUCT DESCRIPTIONThe AD420 is a complete digital to current loop output con-
verter, designed to meet the needs of the industrial control
market. It provides a high precision, fully integrated, low cost
single-chip solution for generating current loop signals in a
compact 24-lead SOIC or PDIP package.
The output current range can be programmed to 4 mA–20 mA,
0 mA–20 mA or an overrange function of 0 mA–24 mA. The
AD420 can alternatively provide a voltage output from a sepa-
rate pin that can be configured to provide 0 V–5 V, 0 V–10 V,5 V or –10 V with the addition of a single external buffer
amplifier.
The 3.3M Baud serial input logic design minimizes the cost of
galvanic isolation and allows for simple connection to com-
monly used microprocessors. It can be used in three-wire or
asynchronous mode and a serial-out pin is provided to allow
daisy chaining of multiple DACs on the current loop side of the
isolation barrier.
The AD420 uses sigma-delta (SD) DAC technology to achieve
16-bit monotonicity at very low cost. Full-scale settling to 0.1%
occurs within 3 ms. The only external components that are re-
quired (in addition to normal transient protection circuitry) are
two low cost capacitors which are used in the DAC output filter.
If the AD420 is going to be used at extreme temperatures and
supply voltages, an external output transistor can be used to
minimize power dissipation on the chip via the “BOOST” pin.
The FAULT DETECT pin signals when an open circuit occurs
in the loop. The on-chip voltage reference can be used to supply
a precision +5 V to external components in addition to the
AD420 or, if the user desires temperature stability exceeding
25 ppm/°C, an external precision reference such as the AD586
can be used as the reference.
The AD420 is available in a 24-lead SOIC and PDIP over the
industrial temperature range of –40°C to +85°C.
PRODUCT HIGHLIGHTSThe AD420 is a single chip solution for generating 4 mA–
20 mA or 0 mA–20 mA signals at the “controller end” of the
current loop.The AD420 is specified with a power supply range
from 12 V to 32 V. Output loop compliance is 0 V to
VCC – 2.5 V.The flexible serial input can be used in three-wire mode
with SPI® or MICROWIRE® microcontrollers, or in asyn-
chronous mode which minimizes the number of control
signals required.The serial data out pin can be used to daisy chain any num-
ber of AD420s together in three-wire mode.At power-up the AD420 initializes its output to the low end
of the selected range.The AD420 has an asynchronous CLEAR pin which sends
the output to the low end of the selected range (0 mA,
4 mA, or 0 V).The AD420 BOOST pin accommodates an external transis-
tor to off-load power dissipation from the chip.The offset of –0.05% and total output error of –0.15% can
be trimmed if desired, using two external potentiometers.
SPI is a registered trademark of Motorola.
MICROWIRE is a registered trademark of National Semiconductor.
AD420–SPECIFICATIONS(TA = TMIN–TMAX, VCC = +24 V, unless otherwise noted)VOUT CHARACTERISTICS
DIGITAL INPUTS
NOTES
1X refers to package designator, R or N.External capacitor selection must be as described in Figure 5.
3Total Output Error includes Offset and Gain Error. Total Output Error and Offset Error are with respect to the Full-Scale Output and are measured with an ideal
+5 V reference. If the internal reference is used, the reference errors must be added to the Offset and Total Output Errors.
4PSRR is measured by varying VCC from 12 V to its maximum 32 V.
ABSOLUTE MAXIMUM RATINGS*VCC to GND
AD420AR/AN-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 V
IOUT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VCC
Digital Inputs to GND . . . . . . . . . . . . . . . . . . .–0.5 V to +7 V
Digital Output to GND . . . . . . . . . . . . .–0.5 V to VLL + 0.3 V
VLL and REF OUT: Outputs Safe for Indefinite Short to Ground
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
Thermal Impedance:
SOIC (R) Package . . . . . . . . . . . . . . . . . . . . . .qJA = 75°C/W
PDIP (N) Package . . . . . . . . . . . . . . . . . . . . . .qJA = 50°C/W
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE*N = Plastic DIP, R = Plastic SOIC.
PIN DESIGNATIONS
NC = NO CONNECT
CAP2
VCC
VLL
FAULT DETECT
RANGE SELECT 2
IOUT
BOOST
CAP1RANGE SELECT 1
CLEAR
LATCH
CLOCK
DATA IN
DATA OUTREF IN
OFFSET TRIM
VOUT
GND
REF OUT
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD420 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Figure 1. Functional Block Diagram
Table I.Truth Table
AD420
Timing Requirements(TA = –408C to +858C, VCC = +12 V to +32 V)
THREE-WIRE INTERFACE
CLOCK
DATA IN
LATCH
DATA OUT
CLOCK
DATA IN
LATCH
DATA OUT
WORD "N"WORD "N + 1"
WORD "N – 1"WORD "N"
(MSB)
B15B14
B13B12B11B10B8B7B6B5B4B3B2B1B0
B15B14B13B12
(LSB)Figure 2.Timing Diagram for Three-Wire Interface
Table II.Timing Specification for Three-Wire Interface
Three-Wire Interface Fast Edges on Digital InputWith a fast rising edge (<10 ns) on one of the serial inputs
(CLOCK, DATA IN, LATCH) while another input is logic
high, the part may be triggered into a test mode and the con-
tents of the data register may become corrupted, which may
result in the output being loaded with an incorrect value. If fast
edges are expected on the digital input lines, it is recommended
that the latch line remain at Logic 0 during serial loading of the
DAC. Similarly, the clock line should remain low during updates
of the DAC via the latch pin. Alternatively, the addition of
small value capacitors on the digital lines will slow down the
edge.
Figure 3. Timing Diagram for Asynchronous Interface
Table III.Timing Specifications for Asynchronous InterfaceAsynchronous Clock Low Time
Asynchronous Clock High Time
Data Stable Width (Critical Clock Edge)
Data Setup Time (Critical Clock Edge)
Data Hold Time (Critical Clock Edge)
ASYNCHRONOUS INTERFACENote in the timing diagram for asynchronous mode operation
each data word is “framed” by a START (0) bit and a STOP
(1) bit. The data timing is with respect to the rising edge of the
CLOCK at the center of each bit cell. Bit cells are 16 clocks
long, and the first cell (the START bit) begins at the first clock
following the leading (falling) edge of the START bit. Thus the
MSB (D15) is sampled 24 clock cycles after the beginning of
the START bit, D14 is sampled at clock number 40, and so on.
During any “dead time” before writing the next word the
DATA IN pin must remain at Logic 1.
The DAC output updates when the STOP bit is received. In
the case of a “framing error” (the STOP bit sampled as a 0) the
AD420 will output a pulse at the DATA OUT pin one clock
period wide during the clock period subsequent to sampling the
STOP bit. The DAC output will not update if a “framing error”
PIN DESCRIPTION
DEFINITIONS OF SPECIFICATIONSRESOLUTION: For 16-bit resolution, 1 LSB = 0.0015% of the
FSR. In the 4 mA–20 mA range 1 LSB = 244 nA.
INTEGRAL NONLINEARITY: Analog Devices defines inte-
gral nonlinearity as the maximum deviation of the actual, ad-
justed DAC output from the ideal analog output (a straight line
drawn from 0 to FS – 1 LSB) for any bit combination. This is
also referred to as relative accuracy.
DIFFERENTIAL NONLINEARITY: Differential nonlinearity
is the measure of the change in the analog output, normalized to
full scale, associated with an LSB change in the digital input code.
Monotonic behavior requires that the differential linearity error be
greater than –1 LSB over the temperature range of interest.
GAIN ERROR:Gain error is a measure of the output error
between an ideal DAC and the actual device output with all 1s
loaded after offset error has been adjusted out.
OFFSET ERROR:Offset error is the deviation of the output
current from its ideal value expressed as a percentage of the full-
scale output with all 0s loaded in the DAC.
DRIFT:Drift is the change in a parameter (such as gain and
offset) over a specified temperature range. The drift temperature
coefficient, specified in ppm/°C, is calculated by measuring the
parameter at TMIN, 25°C, and TMAX and dividing the change in
the parameter by the corresponding temperature change.
CURRENT LOOP VOLTAGE COMPLIANCE:The voltage
compliance is the maximum voltage at the IOUT pin for which
AD420
THEORY OF OPERATIONThe AD420 uses a sigma-delta (SD) architecture to carry out
the digital-to-analog conversion. This architecture is particularly
well suited for the relatively low bandwidth requirements of the
industrial control environment because of its inherent monoto-
nicity at high resolution.
In the AD420 a second order modulator is used to keep com-
plexity and die size to a minimum. The single bit stream from
the modulator controls a switched current source that is then
filtered by two, continuous time resistor-capacitor sections. The
capacitors are the only external components that have to be
added for standard current-out operation. The filtered current is
amplified and mirrored to the supply rail so that the application
simply sees a 4 mA–20 mA, 0 mA–20 mA, or 0 mA–24 mA
current source output with respect to ground. The AD420 is
manufactured on a BiCMOS process that is well suited to imple-
menting low voltage digital logic with high performance and
high voltage analog circuitry.
The AD420 can also provide a voltage output instead of a cur-
rent loop output if desired. The addition of a single external
amplifier allows the user to obtain 0 V–5 V, 0 V–10 V, –5 V, or10 V.
The AD420 has a loop fault detection circuit that warns if the
voltage at IOUT attempts to rise above the compliance range, due
to an open-loop circuit or insufficient power supply voltage. The
FAULT DETECT is an active low open drain signal so that one
can connect several AD420s together to one pull-up resistor for
global error detection. The pull-up resistor can be tied to the
VLL pin, or an external +5 V logic supply.
The IOUT current is controlled by a PMOS transistor and
internal amplifier as shown in the functional block diagram. The
internal circuitry that develops the fault output avoids using a
comparator with “window limits” since this would require an
actual output error before the FAULT DETECT output becomes
active. Instead, the signal is generated when the internal ampli-
fier in the output stage of the AD420 has less than approximately
one volt remaining of drive capability (when the gate of the
output PMOS transistor nearly reaches ground). Thus the
FAULT DETECT output activates slightly before the compli-
ance limit is reached. Since the comparison is made within the
feedback loop of the output amplifier, the output accuracy is
maintained by its open-loop gain, and no output error occurs
before the fault detect output becomes active.
The three-wire digital interface, comprising DATA IN, CLOCK,
and LATCH, interfaces to all commonly used serial micropro-
cessors without the addition of any external glue logic. Data is
loaded into an input register under control of CLOCK and is
loaded to the DAC when LATCH is strobed. If a user wants to
minimize the number of galvanic isolators in an intrinsically safe
application, the AD420 can be configured to run in “asynchro-
nous” mode. This mode is selected by connecting the LATCH
pin to VCC through a current limiting resistor. The data must
then be combined with a start and stop bit to “frame” the infor-
mation and trigger the internal LATCH signal.
Figure 4.Functional Block Diagram
