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AD3554BM
FAST-SETTLING, WIDEBAND, FET-INPUT OP AMP
Dy ANALOG
DEVICES
Fast-Settling, Wideband,
FET-lnput 0p Amp
FEATURES
Very High Slew Rate: 1000V/ps
Fast Settling: 150m max to *0.05%
Gain Bandwidth Ptoduct: 1.7GHz typical
High Output Current: 100mA min ti VOUT = 10V
Full Differential Input
PRODUCT DESCRIPTION
The AD3554 is a FET-input, hybrid operational amplifier
that features an excellent combination of high slew rate, fast
settling time and large gain-bandwidth product. The AD3554
has a full differential input with matched input FETs for low
offset voltage.
The AD3554 can supply t100mA at 10 volts. The slew rate
is 1000V/ps minimum; 1200V/ps is typical. Settling time
to 10.05% of final value is only Lions when configured as an
inverting amplifier. The user can optimize the combination of
bandwidth, slew rate, and settling time for a particular applica-
tion by selecting the external compensation capacitor.
The AD3554 is recommended for any operational ampli-
fier application where speed and bandwidth are important
considerations. The high slew rate and fast settling time make
the AD3554 an excellent choice for use in fast D/A con-
verters, fast current amplifiers, integrators, waveform gener-
ators and multiplexer buffers.
The AD3554 is available in three versions.. the "A" and "B"
are specified over the -25°C to +85°C temperature range and
"s" over the -5 fc to +125°C operating temperature range.
All devices are packaged in the hermetically.sealed T0-3 style
metal can.
The AD3554 is a pin-compatible replacement for 3554 devices
from other manufacturers.
AD3554 FUNCTIONAL BLOCK DIAGRAM
NONINVERTING
/|NPUT E
INVERTING
INPUT 6
T0-3 STY LE
BOTTOM VIEW
PRODUCT HIGHLIGHTS
The high slew rate (1000V/ps min) and fast settling time
to 0.01% (250ns max) make the AD3554 ideal for D/A,
AID, sample-hold, and video instrumentation circuits.
' Laser trimming techniques reduce initial offset voltage to
as low as lmV max (AD3554B), thus eliminating the need
for external nulling in many applications.
' Very high gain-bandwidth product (1.7GHz typical at
A = 1000) makes the AD3554 an ideal choice for high
frequency amplifier applications.
. FET inputs result in a low bias current (50pA max, lOpA
typ) in ahigh gain-bandwidth product operational amplifier,
' Full differential input makes the AD3554 ideal for all
standard operational amplifier applications such as high
speed integrators, differentiators, and high gain amplifiers.
. The 100mA at 10V output makes the AD3554 suitable
for many applications that require high output power,
such as cable drivers. The capacitance of coaxial cable
(e.g., 29pF/foot for RG-58) does not load the AD3554
when the coaxial cable or transmission line is terminated
in its characteristic impedance.
OPERA TIONAL AMPLIFIERS VOL. I, 4- 1 11
SPECIFICATIONS (typical tir TCASE = +25°C and Vs = 115V dc unless otherwise specified)
MODEL ADSSHAM AD3554BM AD3554SM
OPEN LOOP GAIN
No Load 106dB (lOOdB min) . .
RL = 1009 96dB (9thlB min) . .
OUTPUT CHARACTERISTICS
Voltage @10 = t100mA Al IV (nov min) . .
Output Resistance, Open Loop ' f = lOMHz 2on
Current Q vo = :10v tlZSmA (iIOOmA min) . .
FREQUENCY RESPONSE
Bandwidth (OdB, Small Signal, CF = o)' 90MHz (70MB: min) . .
Gain-Bandwidth Product, Cr = 0
_ G = 10V/V 225MHz (150MHz min) . .
G = lOOV/V 725MHz (425MHz min) . .
G = 1000VN 1700MH2 (lOOOMHz min) . .
Full Power Bandwidth, CF = o, Vo = 20V p-p,
RL = 100n 19mm (16MHz min) . .
Slew Rate, CF = 0, Vo = 20V p-p,
RL = 1009 1200V/ps (lOOOV/us min) . .
Settling Time, A = -1, to 11% 60ns . .
to $0.196 120ns . .
to 10.05% 140ns (150ns max) . .
to 20.01% 200ns (250ns max) . .
INPUT OFFSET VOLTAGE
Initial Offset 0.5mV (2.0mV max) 0.2mV (1.0mV max) ..
vs. Temperature 20pV/°C (50pV/°C max) 8;:fo (lSuV/°C max) lZuVI°C (25uV/°C max)
vs. Supply, TA = min to max 80pV/V (SOOuVN max) . a
INPUT BIAS CURRENT
Either Input‘ lOpA (50pA max) . .
Initial Difference 2pA (lOpA max) . .
vs. Supply Voltage lpA/V . .
INPUT IMPEDANCE
Differential to" nll2PF . .
Common Mode tou nll2PF . .
INPUT VOLTAGE RANGE
Max Safe Input Voltage, Diff 1(lvccl-8) . .
Common Mode 1(IVccl-4) . .
Common Mode Rejection, VCM = +7V, -10V 78dB (60dB min) . .
POWER SUPPLY
Rated Performance tlSV . .
Operating t(7 to 18)V . .
Quiescent Current 28mA (45mA max) . .
INPUT NOISE'
Voltage, fo = IHz tMnV Hz (4SOnV/ Hz max) . .
fo = lOHz SOnV Hz 1ti'is'iiiiiffi,iiix) . .
fa = lOOHz zanIJrTi (90nV/ Hz max) . .
fo = lkHz 1snv/s/iE(sonv/v(sT, max) . .
f0 = 10km IvaLrE 05an max) . .
fo = lOOkHz 8nV/ Hz (2snvtsmrmaxy . .
f0 = mm 7nV/s/m i2snws/iiz%ax) . .
fa = 0.3Hz to 10Hz 2ttV p-p (7ttV " max) . .
h, = 10Hz to lMHz BuV rms (MPV rms max) . .
Current, h, = 3H2 to 10Hz 4SfA p-p . .
fre = 10Hz to lMHz 2pA rms . .
TEMPERATURE RANGE
Operating, Rated Performance -2fc to +85°C . -sfc to +125°C
Storage -6s''c to +150°C . .
PACKAGE3 - TO-3 Style (H08C) AD3554AM AD3554BM AD3554SM
'These plumeters are untested md not guaranteed, This specifica-
tion is ambushed to n 90% cotsfidence level.
' Bias Current specifications at guaranteed maximum It either input
It TCAS . 425°C. For higher temperatures. the current doubles
every 1 C.
'see Section 19 for plcluge outline informrtion.
'Specifications am: an ADJSMAM
VOL. I, 4-f 12 OPERA TIONAL AMPLIFIERS
"specirscstior" am: " ADJSS4BM.
Specifications mbiect to clung: without notice.
mu LW VOLYAGE GAIN A ‘I
mo lk mu 100: IM to" TOOM
FREQUENCY - N:
Figure 1. Open Loop Frequency
Romance (Voltage Gain)
soar-S' I
StEW NAT! — VIII:
" oh‘ ' 2 a w 20 " m
COMPENSATION CAVACIYOR Cg - "
Figure 4. Slew Rate " Compensation
" L/ w/ w/
j-_',',,'', / ///,,,,,,
'ii,,, / 4/,
SETTLING YIN! - "
Figure 7. Settling Time vs. Output
Voltage Change (Circuit of Figure 18A)
VOLTAGE GAIN — O
6 Uh IS 20
SUPPLY VOLTAGE - :V
Figure m. Open Loop Gain " Supply
Voltage
to c .5“ "s,. -cc-uw
'i'.'''),., lit
100 " IO! INK lht ‘W wow
MA“ 9
FREOUENCV - N1
Figure 2. Open Loop Frequency
Response (Phase Shift)
CWINSA'ION CMACITON - IF
I 2 s IO 20 so 100
CLOSED LOOP GAIN - V/V
Figure 5. Recommended Compensation
Capacitor w. Closed Loop Gain
nL-mon
- g) ga. mm
Figure 8. Voltage Follower Large
Signal Response
'cii5iss'i," 3:"qu TIME
s, IMMIDTH
" / 's, umnut
s '0 16 "
RELAYIVE VALUE
SWLV VOLTAGE - tV
Figure " Dynamic Characteristics
" Supply Voltage
nl . loan
v, . mv
. llt "" 1
la' w- nzv
mm m ttm I”
F I EOUKNCV - NI
Figure 3. Output Voltage
" Frequency
SETTLING "ME - m
, 2 5 IO 20 so 100
CLOSED LOOP GAON A "
Figure 6. Settling Time w. Closed Loop
Gain (Circuit of Figure 18A)
"XtlIp.er
P'''''''-'''
F igure 9. Voltage Follower Small
Signal Response
SITTLING TIM
w 2.7icr.
' SLEW RATE
a -...---"
g nmmuom
-75 -25 "' '75 025
nmmnule - "C
Figure 12. Dynamic Characteristics
" Temperature
OPERA TIONAL AMPLIFIERS VOL. J, 4-113
' m. I
E - Eco
- CASE "
t , k"
g 2 Amman EM
i 'ss., E w
"ss, w
I "sc t M
o g t o
o " so 75 we 125 loo 1k
TEM'ERATUIE - 'C
Figure M. Power Dissipation
" Temperature
COW MODE REJECI‘U‘ ‘ 1M
o 5 IO "
COMMON MODE INPUY VOLTAGE A V
Figure ttr. Common Mode Rejection
W. Input Voltage
'd, v I
m D2 MP 5082-2311
Vm scnonxv DIODES
a... " '
T v "' "p.".-
Cr 5a
in . "shunt . Icon
OUTPUT
CLOSED LOOP GAIN IS
'REOUENCV - m
Figure M. PSRR w. Frequency
P'''"""'"" _
.. ....
won m 109.: " m m m mu mu
FRIOUENCV -Ml
Figure M. CMRR " Frequency
av 1,..1zs'c ''2siiei'"
u-,,1li';.'i'.:iii-rr;
QUIESCENY SWLV CURRENI’ — «IA
5 10 " 20
SUPPLY VOLTAGE V 1v
Figure 17. Quiescent Supply Current
vs. Supply Voltage
BNC COMMON
COMMON
MALE BNC
CONNECTORS
OlRicTLV
OUTPUT 1EKVRDNIX
PROBE YIP 7AIJ PLUGJN
T E ST JACK
Figure 188. Settling Time Test Circuit Layout
Figure 180. Unity Gain Inverter Settling Time
VOL. I, 4-114 OPERA TIONAL AMPLIFIERS
LAYOUT CONSIDERATIONS
As is the case with any high-speed design, proper layout is
critical to avoid the introduction of unnecessary errors due to
high-frequency coupling and stray capacitance.
Large ground planes should be used whenever possible to
provide a low resistance, low inductance circuit path, as well
as shielding the effects of high-frequency coupling. Sockets
should be avoided, as the increased inter-lead capacitance can
degrade bandwidth. Input and output connections should be
kept as short as practical, particularly to the inverting input,
which is especially sensitive to stray capacitances.
Low value resistors should be used to assure that the time
constants formed with the circuit capacitances will not limit
the amplifier performance. Resistor values less than 5.6kSI
are recommended.
Each power supply lead should be bypassed to ground as close
as possible to the amplifier pins. A 10PF electrolytic or tan-
talum capacitor in parallel with a 0,01pF ceramic capacitor
is recommended.
GROUNDING
Grounding the case will add a slight capacitance to each pin.
Therefore, we recommend leaving the case ungrounded.
In inverting applications we recommend grounding the non-
inverting input rather than connecting it to a bias current
compensating resistor. FET input amplifiers do not require
compensating resistors because of their low input bias cur-
rents.
GUARDING
In high input impedance applications the input terminals may
be surrounded by a conductive path to divert leakage currents.
This guard ring should be connected to a low impedance point
" the input signal potential.
In high frequency applications guarding may not be desirable
as it increases the risk of oscillation due to increased printed
circuit board capacitance.
COMPENSATION
The user can optimize the bandwidth, slew rate, or settling
time by selecting the external frequency compensation ca-
pacitor. No compensation capacitor is required for closed loop
gains above 50 and when the load capacitance is less than
lOOpF. When driving capacitive loads greater than 470pF, in
low closed loop gain configurations, connect a 1000pF ca-
pacitor between pin 8 and the positive supply. The perform-
ance may be improved by connecting a small resistor in series
with the output and a small capacitor from pin 1 to 5. See
Typical Circuits.
The flat high frequency response of the AD3554 may be pre-
served and any high frequency peaking avoided by connecting
a small capacitor in parallel with the feedback resistor. This
capacitor will compensate for the closed loop, high frequency,
transfer function zero that results from the time constant
formed by the input capacitance of the amplifier, typically
2pF, and the input and feedback resistors. Using small resistor
values will keep the break frequency of this zero sufficiently
high, avoiding peaking and preserving the phase margin.
The selected compensation capacitor may be a trimmer, a
fixed capacitor or a planned PC board capacitance. The
capacitance value is strongly dependent on circuit layout
and closed loop gain.
SHORT CIRCUIT PROTECTION
The AD3554 is short circuit protected for continuous output
shorts to ground. Output shorts to either supply will destroy
the device.
HEAT SINKING
The ADS 554 does not require heat sinking for most applica-
tions. However, at extreme temperature and full load
conditions a heat sink will be necessary as indicated in the
maximum power dissipation curve. We recommend connecting
the heat sink to the amplifier case and keeping the combine
tion ungrounded.
TYPICAL CIRCUITS
''THESE COMPONENTS MAY BE ELIMINATED WHEN NOT
DRIVING LARGE CAPACITIVE LOADS.
Figure 19. Unity Gain Inverter
F-o Vour
'THESE COMPONENTS MAY BE ELIMINATED WHEN NOT
DRIVING LARGE CAPACITIVE LOADS.
Figure 20. Folio wer
OPERA TIONAL AMPLIFIERS VOL. I, 4-It5
