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AD2S90AP
Low Cost, Complete 12-Bit Resolver-to-Digital Converter
FUNCTIONAL BLOCK DIAGRAM
SIN
SIN LO
COS
NMC
SCLK
DATA
REF
ERROR
AMPLIFIER
CLK
U/D
ANGLE
COS LO
REV. D
FEATURES
Complete Monolithic Resolver-to-Digital Converter
Incremental Encoder Emulation (1024-Line)
Absolute Serial Data (12-Bit)
Differential Inputs
12-Bit Resolution
Industrial Temperature Range
20-Lead PLCC
Low Power (50 mW)
APPLICATIONS
Industrial Motor Control
Servo Motor Control
Industrial Gauging
Encoder Emulation
Automotive Motion Sensing and Control
Factory Automation
Limit Switching
GENERAL DESCRIPTION
The AD2S90 is a complete 12-bit resolution tracking resolver-
to-digital converter. No external components are required to
operate the device.
The converter accepts 2 V rms – 10% input signals in the rangekHz–20 kHz on the SIN, COS and REF inputs. A Type II
servo loop is employed to track the inputs and convert the input
SIN and COS information into a digital representation of the
input angle. The bandwidth of the converter is set internally atkHz within the tolerances of the device. The guaranteed maxi-
mum tracking rate is 500 rps.
Angular position output information is available in two forms,
absolute serial binary and incremental A quad B.
The absolute serial binary output is 12-bit (1 in 4096). The data
output pin is high impedance when Chip Select CS is logic HI.
This allows the connection of multiple converters onto a com-
mon bus. Absolute angular information in serial pure binary
form is accessed by CS followed by the application of an exter-
nal clock (SCLK) with a maximum rate of 2 MHz.
The encoder emulation outputs A, B and NM continuously
produce signals equivalent to a 1024 line encoder. When de-
coded this corresponds to 12 bits of resolution. Three common
north marker pulsewidths are selected via a single pin (NMC).
An analog velocity output signal provides a representation of
velocity from a rotating resolver shaft traveling in either a clock-
wise or counterclockwise direction.
The AD2S90 operates on –5 V dc – 5% power supplies and is
fabricated on Analog Devices’ Linear Compatible CMOS pro-
cess (LC2MOS). LC2MOS is a mixed technology process that
combines precision bipolar circuits with low power CMOS logic
circuits.
PRODUCT HIGHLIGHTS
Complete Resolver-Digital Interface.The AD2S90 provides
the complete solution for digitizing resolver signals (12-bit reso-
lution) without the need for external components.
Dual Format Position Data.Incremental encoder emulation
in standard A QUAD B format with selectable North Marker
width. Absolute serial 12-bit angular binary position data
accessed via simple 3-wire interface.
Single High Accuracy Grade in Low Cost Package.–10.6 arc
minutes of angular accuracy available in a 20-lead PLCC.
Low Power.Typically 50mW power consumption.
Low Cost, Complete 12-Bit
Resolver-to-Digital Converter
ACCURACY
SERIAL CLOCK (SCLK)
NOTESIf the tolerance on signal inputs = –5%, then CMV = 200 mV.1 LSB = 5.3 arc minute.Specified at constant temperature.
AD2S90–SPECIFICATIONS
(VDD = +5V 6 5%, VSS = –5V 6 5%, AGND = DGND = 0V, TA = –408C to +858C unless
otherwise noted)
NOTESCLK can only be applied after t2 has elapsed.
(VDD = +5V 6 5%, VSS = –5V 6 5%, AGND = DGND = 0V, TA = –408C to +858C unless
otherwise noted)TIMING CHARACTERISTICS1, 2
Figure 1.Serial Interface
NOTESTiming data are not 100% production tested. Sample tested at +25°C only to ensure conformance to data sheet limits. Logic output timing tests carried out using
10 pF, 100 kW load.Capacitance of data pin in high impedance state = 15 pF.
Figure 2.Incremental Encoder
Figure 3.DIR/CLKOUT/A, B and NM Timing
AD2S90
RECOMMENDED OPERATING CONDITIONS
Power Supply Voltage (VDD – VSS) . . . . . . . . . .–5 V dc – 5%
Analog Input Voltage (SIN, COS & REF) . . . . .2 V rms – 10%
Signal and Reference Harmonic Distortion . . . . . . . . . . . .10%
Phase Shift between Signal and Reference . . . . . . . . . . . . .–10°
Ambient Operating Temperature Range
Industrial (AP) . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
ABSOLUTE MAXIMUM RATINGS*
VDD to AGND . . . . . . . . . . . . . . . . . . . .–0.3 V dc to +7.0 V dc
VSS to AGND . . . . . . . . . . . . . . . . . . . .+0.3 V dc to –7.0 V dc
AGND to DGND . . . . . . . . . . . .–0.3 V dc to VDD + 0.3 V dc
Analog Inputs to AGND
REF . . . . . . . . . . . . . . . . . .VSS – 0.3 V dc to VDD + 0.3 V dc
SIN, SIN LO . . . . . . . . . . .VSS – 0.3 V dc to VDD + 0.3 V dc
COS, COS LO . . . . . . . . . .VSS – 0.3 V dc to VDD + 0.3 V dc
Analog Output to AGND
VEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VSS to VDD
Digital Inputs to DGND, CSB,
SCLK, RES . . . . . . . . . . . . . . .–0.3 V dc to VDD + 0.3 V dc
Digital Outputs to DGND, NM, A, B,
DIR, CLKOUT DATA . . . . . .–0.3 V dc to VDD + 0.3 V dc
Operating Temperature Range
Industrial (AP) . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . .300°C
Power Dissipation to +75°C . . . . . . . . . . . . . . . . . . . .300 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . .10mW/°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
CAUTION
The AD2S90 features an input protection circuit consisting of large “distributed” diodes and
polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and
PIN DESCRIPTIONS
PIN CONFIGURATION
For more information on the operation of the converter, see
Circuit Dynamics section.
Figure 4.Electrical and Physical Resolver Representation
Connecting The Converter
Refer to Figure 4. Positive power supply VDD = +5V dc – 5%
should be connected to Pin 13 & Pin 14 and negative power
supply VSS = –5 V dc – 5% to Pin 12. Reversal of these power
supplies will destroy the device. S3 (SIN) and S2 (COS)
from the resolver should be connected to the SIN and COS pins
of the converter. S1 (SIN) and S4 (COS) from the resolver
should be connected to the SINLO and COSLO pins of the
converter. The maximum signal level of either the SIN or COS
resolver outputs should be 2 V rms – 10%. The AD2S90
AGND pin is the point at which all analog signal grounds should
be star connected. The SIN LO and COS LO pins on the
AD2S90 should be connected to AGND. Separate screened
twisted cable pairs are recommended for all analog inputs SIN,
COS, and REF. The screens should terminate at the converter
AGND pin.
North marker width selection is controlled by Pin 15, NMC.
Application of VDD, 0V, or VSS to NMC will select standard
90°, 180° and 360° pulsewidths. If unconnected, the NM pulse
defaults to 90°. For a more detailed description of the output
formats available see the Position Output section.
RESOLVER FORMAT SIGNALS
A resolver is a rotating transformer which has two stator wind-
ings and one rotor winding. The stator windings are displaced
mechanically by 90° (see Figure 4). The rotor is excited with an
ac reference. The amplitude of subsequent coupling onto the
stator windings is a function of the position of the rotor (shaft)
relative to the stator. The resolver, therefore, produces two
output voltages (S3–S1, S2–S4) modulated by the SINE and
COSINE of shaft angle. Resolver format signals refer to the
signals derived from the output of a resolver. Equation 1 illus-
trates the output form.
S3–S1 = EO SIN wt • SINq
S2–S4 = EO SIN wt • COSq (1)
where:q = shaft angle
SIN wt = rotor excitation frequency
EO = rotor excitation amplitude
Principle of Operation
The AD2S90 operates on a Type 2 tracking closed-loop prin-
ciple. The output continually tracks the position of the resolver
without the need for external convert and wait states. As the
transducer moves through a position equivalent to the least
significant bit weighting, the output is updated by one LSB.
On the AD2S90, CLKOUT updates corresponding to one LSB
increment. If we assume that the current word state of the
up-down counter is f, S3–S1 is multiplied by COS f and S2–S4
is multiplied by SIN f to give:
EO SIN wt • SIN q COSf
EO SIN wt • COS q SINf(2)
An error amplifier subtracts these signals giving:
EO SIN q • (SIN q COS f – COS q SIN f)
EO SIN wt • SIN (q – f)(3)
where (q – f) = angular error
A phase sensitive detector, integrator and voltage controlled
oscillator (VCO) form a closed loop system which seeks to null
sin (q – f). When this is accomplished the word state of the
up/down counter, f, equals within the rated accuracy of the
converter, the resolver shaft angle q.
+5V
–5V
0V (POWER GROUND)
AD2S90
ABSOLUTE POSITION OUTPUT
SERIAL INTERFACE
Absolute angular position is represented by serial binary data
and is extracted via a three-wire interface, DATA, CS and
SCLK. The DATA output is held in a high impedance state
when CS is HI.
Upon the application of a Logic LO to the CS pin, the DATA
output is enabled and the current angular information is trans-
ferred from the counters to the serial interface. Data is retrieved
by applying an external clock to the SCLK pin. The maximum
data rate of the SCLK is 2MHz. To ensure secure data retrieval
it is important to note that SCLK should not be applied until a
minimum period of 600 ns after the application of a Logic LO
to CS. Data is then clocked out, MSB first, on successive nega-
tive edges of the SCLK; 12 clock edges are required to extract
the full 12 bits of data. Subsequent negative edges greater than
the defined resolution of the converter will clock zeros from the
data output if CS remains in a low state.
If a resolution of less than 12 bits is required, the data access
can be terminated by releasing CS after the required number of
bits have been read.
Figure 6.Serial Read Cycle
CS can be released a minimum of 100 ns after the last negative
edge. If the user is reading data continuously, CS can be reap-
plied a minimum of 250 ns after it is released (see Figure 6).
The maximum read time is given by: (12-bits read @ 2 MHz)
Max RD Time = [600 + (12 · 500) + 600 + 100] = 7.30ms.
INCREMENTAL ENCODER OUTPUTS
The incremental encoder emulation outputs A, B and NM are
free running and are always valid, providing that valid resolver
format input signals are applied to the converter.
The AD2S90 emulates a 1024-line encoder. Relating this to
converter resolution means one revolution produces 1024 A, B
pulses. B leads A for increasing angular rotation (i.e., clockwise
direction). The addition of the DIR output negates the need for
external A and B direction decode logic. DIR is HI for increas-
ing angular rotation.
The north marker pulse is generated as the absolute angular
position passes through zero. The AD2S90 supports the three
industry standard widths controlled using the NMC pin. Figure
7 details the relationship between A, B and NM. The width of
NM is defined relative to the A cycle.
Figure 7.A, B and NM Timing
Unlike incremental encoders, the AD2S90 encoder output is
not subject to error specifications such as cycle error, eccentric-
ity, pulse and state width errors, count density and phase f.
The maximum speed rating, n, of an encoder is calculated from
its maximum switching frequency, fMAX, and its ppr (pulses per
revolution).
The AD2S90 A, B pulses are initiated from CLKOUT which
has a maximum frequency of 2.048 MHz. The equivalent
encoder switching frequency is:
1/4 · 2.048MHz = 512 kHz (4 updates = 1 pulse)
At 12 bits the ppr = 1024, therefore the maximum speed, n, of
the AD2S90 is:
This compares favorably with encoder specifications where fMAX
is specified from 20 kHz (photo diodes) to 125 kHz (laser based)
depending on the light system used. A 1024 line laser-based
encoder will have a maximum speed of 7300 rpm.
The inclusion of A, B outputs allows the AD2S90 + resolver
solution to replace optical encoders directly without the need to
change or upgrade existing application software.

Partno	Mfg	Dc	Qty	Available	Descript
AD2S90AP	ADI	N/a	92	avai	Low Cost, Complete 12-Bit Resolver-to-Digital Converter