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AD2S83APZ , Variable Resolution, Resolver-to-Digital Converter
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AD2S83AP-AD2S83IP
Variable Resolution, Resolver-to-Digital Converter
REV.D
Variable Resolution,
Resolver-to-Digital Converter
GENERAL DESCRIPTIONThe AD2S83 is a monolithic 10-, 12-, 14- or 16-bit tracking
resolver-to-digital converter.
The converter allows users to select their own resolution and dy-
namic performance with external components. The converter allows
users to select the resolution to be 10, 12, 14 or 16 bits and to
track resolver signals rotating at up to 1040 revs per second
(62,400 rpm) when set to 10-bit resolution.
The AD2S83 converts resolver format input signals into a paral-
lel natural binary digital word using a ratiometric tracking con-
version method. This ensures high noise immunity and tolerance of
long leads allowing the converter to be located remote from the
resolver.
The position output from the converter is presented via 3-state
output pins which can be configured for operations with 8- or
16-bit bus. BYTE SELECT, ENABLE and INHIBIT pins
ensure easy data transfer to 8- and 16-bit data bus, and outputs
are provided to allow for cycle or pitch counting in external
counters.
A precise analog signal proportional to velocity is also available
and will replace a tachogenerator.
The AD2S83 operates over reference frequencies in the range
0 Hz to 20,000 Hz.
PRODUCT HIGHLIGHTS
High Accuracy Velocity Output.A precision analog velocity
signal with a typical linearity of –0.1% and reversion error less
than –0.3% is generated by the AD2S83. The provision of this
signal removes the need for mechanical tachogenerators used in
servo systems to provide loop stabilization and speed control.
Resolution Set by User.Two control pins are used to select
the resolution of the AD2S83 to be 10, 12, 14 or 16 bits allow-
ing optimum resolution for each application.
Ratiometric Tracking Conversion.This technique provides
continuous output position data without conversion delay. It
also provides noise immunity and tolerance of harmonic distor-
tion on the reference and input signals.
Dynamic Performance Set by the User.By selecting exter-
nal resistor and capacitor values the user can determine band-
width, maximum tracking rate and velocity scaling of the
converter to match the system requirements. The component
values are easy to select using the free component selection
software design aid.
MODELS AVAILABLEInformation on the models available is given in the Ordering
Guide.
FUNCTIONAL BLOCK DIAGRAMFEATURES
Tracking R/D Converter
High Accuracy Velocity Output
High Max Tracking Rate 1040 RPS (10 Bits)
44-Lead PLCC Package
10-, 12-, 14- or 16-Bit Resolution Set by User
Ratiometric Conversion
Stabilized Velocity Reference
Dynamic Performance Set by User
Industrial Temperature Range
APPLICATIONS
DC and AC Servo Motor Control
Process Control
Numerical Control of Machine Tools
Robotics
Axis Control
AD2S83–SPECIFICATIONSREFERENCE INPUT (REF)
PERFORMANCE
VELOCITY SIGNAL
DIGITAL POSITION
INHIBIT
(6VS = 612 V dc 6 5%; VL = +5 V dc 6 10%; TA = –408C to +858C)
DATA LOAD
BUSY
RIPPLE CLOCK
DIGITAL INPUTS
DIGITAL INPUTS
DIGITAL INPUTS
DIGITAL OUTPUTS
NOTESAngular accuracy is not guaranteed <50 Hz reference frequency.Linearity derates from 500 kHz–1000 kHz @ 0.0017%/kHz.Refer to Definition of Linearity, “The AD2S83 as a Silicon Tachogenerator.”Worst case reversion error at temperature extremes.
AD2S83
AD2S83–SPECIFICATIONSINTEGRATOR
VCO
POWER SUPPLIES
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.
Specification subject to change without notice.
(6VS = 612 V dc 6 5%; VL = +5 V dc 6 10%; TA = –408C to +858C)
ORDERING GUIDE
PIN FUNCTION DESCRIPTIONS
ABSOLUTE MAXIMUM RATINGS1 (with respect to GND)+VS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V dc
–VS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –13 V dc
+VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VS
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V to –VS
SIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V to –VS
COS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V to –VS
Any Logical Input . . . . . . . . . . . . . . . . . . –0.4 V dc to +VL dc
Demodulator Input . . . . . . . . . . . . . . . . . . . . . . . +13 V to –VS
Integrator Input . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V to –VS
VCO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V to –VS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mW
Operating Temperature
Industrial (AP, IP) . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
CAUTIONAbsolute Maximum Ratings are those values beyond which damage to the device
may occur.Correct polarity voltages must be maintained on the +VS and –VS pins.
RECOMMENDED OPERATING CONDITIONSPower Supply Voltage (+VS, –VS) . . . . . . . . . .–12 V dc – 5%
Power Supply Voltage VL . . . . . . . . . . . . . . . . .+5 V dc – 10%
Analog Input Voltage (SIN and COS) . . . . . . . .2 V rms – 10%
Analog Input Voltage (REF) . . . . . . . . . . . . . .1 V to 8 V peak
Signal and Reference Harmonic Distortion . . . . . . .10% (max)
PhaseShiftBetweenSignalandReference . . .–10 Degrees(max)
Ambient Operating Temperature Range
Industrial (AP, IP) . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
PIN CONFIGURATION
BYTE SELECT
ESD SENSITIVITYThe AD2S83 features an input protection circuit consisting of large “distributed” diodes and
polysilicon series resistors to dissipate both high energy discharge (Human Body Model) and fast, low
AD2S83
Bit Weight Table
CONNECTING THE CONVERTERThe power supply voltages connected to +VS and –VS pins
should be +12 V dc and –12 V dc and must not be reversed.
The voltage applied to VL can be +5 V dc to +VS.
It is recommended that the decoupling capacitors are connected
in parallel between the power lines +VS, –VS and ANALOG
GROUND adjacent to the converter. Recommended values are
100 nF (ceramic) and 10 mF (tantalum). Also capacitors of
100 nF and 10 mF should be connected between +VL and
DIGITAL GROUND adjacent to the converter.
When more than one converter is used on a card, separate de-
coupling capacitors should be used for each converter.
The resolver connections should be made to the SIN and COS
inputs, REFERENCE INPUT and SIGNAL GROUND as
shown in Figure 11 and described in the Connecting the
Resolver section.
The two signal ground wires from the resolver should be joined
at the SIGNAL GROUND pin of the converter to minimize the
coupling between the sine and cosine signals. For this reason it
is also recommended that the resolver is connected using indi-
vidually screened twisted pair cables with the sine, cosine and
reference signals twisted separately.
SIGNAL GROUND and ANALOG GROUND are connected
internally. ANALOG GROUND and DIGITAL GROUND
must be connected externally and as close to the converter as
possible.
The external components required should be connected as
shown in Figure 1.
CONVERTER RESOLUTIONTwo major areas of the AD2S83 specification can be selected by
the user to optimize the total system performance. The resolu-
tion of the digital output is set by the logic state of the inputs
SC1 and SC2 to be 10, 12, 14 or 16 bits; and the dynamic char-
acteristics of bandwidth and tracking rate are selected by the
choice of external components.
The choice of the resolution will affect the values of R4 and R6
which scale the inputs to the integrator and the VCO respec-
tively (see Component Selection section). If the resolution is
changed, then new values of R4 and R6 must be switched into
the circuit.
Note:When changing resolution under dynamic conditions, do
it when the BUSY is low, i.e., when data is not changing.
RIPPLE
CLOCK
VELOCITY
SIGNAL
REFERENCE
I/PSC1SC2DATA
BYTE
+12V
–12V
GND
COS
SIG GND
SINENABLE
CONVERTER OPERATIONWhen connected in a circuit such as shown in Figure 10, the
AD2S83 operates as a tracking resolver-to-digital converter.
The output will automatically follow the input for speeds up to
the selected maximum tracking rate. No convert command is
necessary as the conversion is automatically initiated by each
LSB increment, or decrement, of the input. Each LSB change of
the converter initiates a BUSY pulse.
The AD2S83 is remarkably tolerant of input amplitude and
frequency variation because the conversion depends only on the
ratio of the input signals. Consequently there is no need for
accurate, stable oscillator to produce the reference signal. The
inclusion of the phase sensitive detector in the conversion loop
ensures high immunity to signals that are not phase or frequency
coherent or are in quadrature with the reference signal.
SIGNAL CONDITIONINGThe amplitude of the SINE and COSINE signal inputs should
be maintained within 10% of the nominal values if full perfor-
mance is required from the velocity signal.
The digital position output is relatively insensitive to amplitude
variation. Increasing the input signal levels by more than 10%
will result in a loss in accuracy due to internal overload. Reduc-
ing levels will result in a steady decline in accuracy. With the
signal levels at 50% of the correct value, the angular error will
increase to an amount equivalent to 1.3 LSB. At this level the
repeatability will also degrade to 2 LSB and the dynamic re-
sponse will also change, since the dynamic characteristics are
proportional to the signal level.
The AD2S83 will not be damaged if the signal inputs are ap-
plied to the converter without the power supplies and/or the
reference.
REFERENCE INPUTThe amplitude of the reference signal applied to the converter’s
input is not critical, but care should be taken to ensure it is kept
within the recommended operating limits.
The AD2S83 will not be damaged if the reference is supplied to
the converter without the power supplies and/or the signal
inputs.
HARMONIC DISTORTIONThe amount of harmonic distortion allowable on the signal and
reference lines is 10%.
Square waveforms can be used but the input levels should be
adjusted so that the average value is 1.9 V rms. (For example, a
square wave should be 1.9 V peak.) Triangular and sawtooth
waveforms should have a amplitude of 2 V rms.
Note: The figure specified of 10% harmonic distortion is for
calibration convenience only.
POSITION OUTPUTThe resolver shaft position is represented at the converter out-
put by a natural binary parallel digital word. As the digital posi-
tion output of the converter passes through the major carries,
i.e., all “1s” to all “0s” or the inverse, a RIPPLE CLOCK (RC)
The direction of input rotation is indicated by the DIRECTION
(DIR) logic output. This direction data is always valid in ad-
vance of a RIPPLE CLOCK pulse and, as it is internally
latched, only changing state (1 LSB min change in input) with a
corresponding change in direction.
Both the RIPPLE CLOCK pulse and the DIRECTION data
are unaffected by the application of the INHIBIT. The static
positional accuracy quoted is the worst case error that can occur
over the full operating temperature excluding the effects of
offset signals at the INTEGRATOR INPUT (which can be
trimmed out—see Figure 1), and with the following conditions:
input signal amplitudes are within 10% of the nominal; phase
shift between signal and reference is less than 10 degrees.
These operating conditions are selected primarily to establish a
repeatable acceptance test procedure which can be traced to
national standards. In practice, the AD2S83 can be used well
outside these operating conditions providing the above points
are observed.
VELOCITY SIGNALThe tracking converter technique generates an internal signal at
the output of the integrator (INTEGRATOR OUTPUT) that is
proportional to the rate of change of the input angle. This is a
dc analog output referred to as the VELOCITY signal.
It is recommended that the velocity output be buffered.
The sense is positive for an increasing angular input and nega-
tive for decreasing angular input. The full-scale velocity output
is –8 V dc. The output velocity scaling and tracking rate are a
function of the resolution of the converter; this is summarized
below.
(Velocity O/P = –8 V dc nominal)
The output velocity can be suitably scaled and used to replace a
conventional DC tachogenerator. For more detailed information
see the AD2S83 as a Silicon Tachogenerator section.
DC ERROR SIGNALThe signal at the output of the phase sensitive detector
(DEMODULATOR OUTPUT) is the signal to be nulled by
the tracking loop and is, therefore, proportional to the error
between the input angle and the output digital angle. As the
converter is a Type 2 servo loop, the demodulator output signal
will increase if the output fails to track the input for any reason.
This is an indication that the input has exceeded the maximum
tracking rate of the converter or, due to some internal or exter-
nal malfunction, the converter is unable to reach a null. By con-
necting two external comparators, this voltage can be used as a
“built-in-test.”
AD2S83
COMPONENT SELECTIONThe following instructions describe how to select the external
components for the converter in order to achieve the required
bandwidth and tracking rate. In all cases the nearest “preferred
value” component should be used, and a 5% tolerance will not
degrade the overall performance of the converter. Care should
be taken that the resistors and capacitors will function over the
required operating temperature range. The components should
be connected as shown in Figure 1.
Free PC compatible software is available to help users select theoptimum component values for the AD2S83, and display the transfer
gain, phase and small step response.
For more detailed information and explanation, see the Circuit
Functions and Dynamic Performance section.
1. HF Filter (R1, R2, C1, C2)
The function of the HF filter is to remove any dc offset and
to reduce the amount of noise present on the signal inputs to
the AD2S83, reaching the Phase Sensitive Detector and
affecting the outputs. R1 and C2 may be omitted—in which
case R2 = R3 and C1 = C3, calculated below—but their use
is particularly recommended if noise from switch mode power
supplies and brushless motor drive is present.
Values should be chosen so that
and fREF = Reference Frequency (Hz)
This filter gives an attenuation of three times at the input to
the phase sensitive detector.Gain Scaling Resistor (R4) (See Phase Sensitive Demodulator
section.)
If R1, C2 are fitted then:
where 100 · 10–9 = current/LSB
If R1, C2 are not fitted then:
where EDC= 160 · 10 for 10 bits resolution
= 40 · 10–3 for 12 bits
= 10 · 10–3 for 14 bits
= 2.5 · 10–3 for 16 bits
= Scaling of the DC ERROR in volts/LSBAC Coupling of Reference Input (R3, C3)
Select R3 and C3 so that there is no significant phase shift at
the reference frequency. That is,
Maximum Tracking Rate (R6)
The VCO input resistor R6 sets the maximum tracking rate
of the converter and hence the velocity scaling as at the max
tracking rate, the velocity output will be 8 V.
Decide on your maximum tracking rate, “T,” in revolutions
per second. When setting the value for R6, it should be
remembered that the linearity of the velocity output is
specified across 0 kHz–500 kHz and 500 kHz–1000 kHz.
The following conversion can be used to determine the
corresponding rps:
Note that “T” must not exceed the maximum tracking rate or
1/16 of the reference frequency.
where n= bits per revolution
= 1,024 for 10 bits resolution
= 4,096 for 12 bits
= 16,384 for 14 bits
= 65,536 for 16 bitsClosed-Loop Bandwidth Selection (C4, C5, R5)Choose the closed-loop bandwidth (fBW) required
ensuring that the ratio of reference frequency to band-
width does not exceed the following guidelines:
ResolutionRatio of Reference Frequency/Bandwidth2.5: 14: 16: 17.5: 1
Typical values may be 100 Hz for a 400 Hz reference fre-
quency and 500 Hz to 1000 Hz for a 5 kHz reference
frequency.Select C4 so that
with R6 in W and fBW, in Hz selected above.C5 is given by
R5 is given by
VCO Phase Compensation
The following values of C6 and R7 should be connected as
close as possible to the VCO output, Pin 41.VCO Optimization
To optimize the performance of the VCO a capacitor, C7,
Offset AdjustOffsets and bias currents at the integrator input can cause an
additional positional offset at the output of the converter of
1 arc minute typical, 5.3 arc minutes maximum. If this can be
tolerated, then R8 and R9 can be omitted from the circuit.
If fitted, the following values of R8 and R9 should be used:
To adjust the zero offset, ensure the resolver is disconnected
and all the external components are fitted. Connect the COS
pin to the REFERENCE INPUT and the SIN pin to the
SIGNAL GROUND and with the power and reference ap-
plied, adjust the potentiometer to give all “0s” on the digital
output bits.
The potentiometer may be replaced with select on test resistors
if preferred.
DATA TRANSFERTo transfer data the INHIBIT input should be used. The data
will be valid 490 ns after the application of a logic “LO” to the
INHIBIT. This is regardless of the time when the INHIBIT is
applied and allows time for an active BUSY to clear. By using
the ENABLE input the two bytes of data can be transferred
after which the INHIBIT should be returned to a logic “HI”
state to enable the output latches to be updated.
BUSY OutputThe validity of the output data is indicated by the state of the
BUSY output. When the input to the converter is changing, the
signal appearing on the BUSY output is a series of pulses at
TTL level. A BUSY pulse is initiated each time the input moves
by the analog equivalent of one LSB and the internal counter is
incremented or decremented.
INHIBIT InputThe INHIBIT logic input only inhibits the data transfer from
the up-down counter to the output latches and, therefore, does
not interrupt the operation of the tracking loop. Releasing the
INHIBIT automatically generates a BUSY pulse to refresh the
output data.
ENABLE InputThe ENABLE input determines the state of the output data. A
logic “HI” maintains the output data pins in the high imped-
ance condition, and the application of a logic “LO” presents the
data in the latches to the output pins. The operation of the
ENABLE has no effect on the conversion process.
BYTE SELECT InputThe BYTE SELECT input selects the byte of the position data
to be presented at the data output DB1 to DB8. The least sig-
nificant byte will be presented on data output DB9 to DB16
(with the ENABLE input taken to a logic “LO”) regardless of
the state of the BYTE SELECT pin. Note that when the
AD2S83 is used with a resolution less than 16 bits the unused
data lines are pulled to a logic “LO.” A logic “HI” on the BYTE
SELECT input will present the eight most significant data bits
on data output DB1 and DB8. A logic “LO” will present the
least significant byte on data outputs 1 to 8, i.e., data outputs
1 to 8 will duplicate data outputs 9 to 16.
The operation of the BYTE SELECT has no effect on the con-
version process of the converter.
RIPPLE CLOCKAs the output of the converter passes through the major carry,
i.e., all “1s” to all “0s” or the converse, a positive going edge on
the RIPPLE CLOCK (RC) output is initiated indicating that a
revolution, or a pitch, of the input has been completed.
The minimum pulsewidth of the ripple clock is 300 ns. RIPPLE
CLOCK is normally set high before a BUSY pulse and resets
before the next positive going edge of the next BUSY pulse.
The only exception to this is when DIR changes while the
RIPPLE CLOCK is high. Resetting of the RIPPLE clock will
only occur if the DIR remains stable for two consecutive posi-
tive BUSY pulse edges.
If the AD2S83 is being used in a pitch and revolution counting
application, the ripple and busy will need to be gated to prevent
false decrement or increment (see Figure 2).
RIPPLE CLOCK is unaffected by INHIBIT.
5K1
BUSY
RIPPLE
CLOCK
TO COUNTER
(CLOCK)
NOTE: DO NOT USE ABOVE CCT WHEN INHIBIT IS LOW.Figure 2.Diode Transistor Logic Nand Gate
AD2S83Figure 3.Digital Timing
*ns
