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AD2S1200WST-AD2S1200YST
12-Bit R/D Converter with Reference Oscillator
12-Bit R/D Converter
with Reference Oscillator
Rev. 0
FEATURES
Complete monolithic R/D converter
Parallel and serial 12-bit data ports
System fault detection
Absolute position and velocity outputs
Differential inputs
±11 arc minutes of accuracy
1,000 rps maximum tracking rate, 12-bit resolution
Incremental encoder emulation (1,024 pulses/rev)
Programmable sinusoidal oscillator on-board
Compatible with DSP and SPI® interface standards
204.8 kHz square wave output
Single-supply operation (5.00 V ± 5%) −40°C to +125°C temperature rating
44-lead LQFP package
4 kV ESD protection
GENERAL DESCRIPTION The AD2S1200 is a complete 12-bit resolution tracking resolver-
to-digital converter, integrating an on-board programmable
sinusoidal oscillator that provides sine wave excitation for
resolvers. An external 8.192 MHz crystal is required to provide
a precision time reference. This clock is internally divided to
generate a 4.096 MHz clock to drive all the peripherals.
The converter accepts 3.6 V p-p ± 10% input signals, in the
range of 10 kHz to 20 kHz on the Sin and Cos inputs. A Type II
servo loop is employed to track the inputs and convert the input
Sin and Cos information into a digital representation of the
input angle and velocity. The bandwidth of the converter is set
internally to 1.7 kHz with an external 8.192 MHz crystal. The
maximum tracking rate is 1,000 rps.
FUNCTIONAL BLOCK DIAGRAM 001
SinLO
SinCosLO
Cos
EXC
EXC
SAMPLE
CPO
REFBYPREFOUTFS1FS2XTALOUTCLKIN(8.192MHz)
DOS
LOT
DIR
DB11SOSOERDVELDB10SCLKDB9–DB0Figure 1.
APPLICATIONS
Electric power steering
Electric vehicles
Integrated starter generator/alternator
Encoder emulation
Automotive motion sensing and control
PRODUCT HIGHLIGHTS Complete Resolver-to-Digital Interface: The AD2S1200
provides the complete solution for digitizing resolver
signals (12-bit resolution) with on-board programmable
sinusoidal oscillator. Ratiometric Tracking Conversion: This technique
provides continuous output position data without
conversion delay. It also provides noise immunity and
tolerance of harmonic distortion on the reference and
input signals. Triple Format Position Data: Absolute 12-bit angular
binary position data accessed either via a 12-bit parallel
port or via a 3-wire serial interface. Incremental encoder
emulation in standard A QUAD B format, with direction
output is available. Digital Velocity Output: 12-bit signed digital velocity,
twos complement format, accessed either via a 12-bit
parallel port or via a 3-wire serial interface. Programmable Excitation Frequency: Excitation fre-
quency easily programmable to 10 kHz, 12 kHz, 15 kHz, or
20 kHz by using the frequency select pins. System Fault Detection: A fault detection circuit will
detect any loss of resolver signals, out of range input
signals, input signal mismatch, or loss of position tracking.
TABLE OF CONTENTS
AD2S1200–Specifications................................................................4
Absolute Maximum Ratings............................................................6
ESD Caution..................................................................................6
Pin Configuration and Function Descriptions.............................7
Resolver Format Signals...................................................................8
Principle of Operation......................................................................9
Fault Detection Circuit.................................................................9
Connecting the Converter.........................................................11
Absolute Position and Velocity Output....................................12
Parallel Interface..........................................................................12
Serial Interface.............................................................................14
Incremental Encoder Outputs...................................................16
On-Board Programmable Sinusoidal Oscillator.....................16
Supply Sequencing and Reset....................................................17
Charge Pump Output.................................................................17
Circuit Dynamics............................................................................18
AD2S1200 Loop Response Model............................................18
Sources of Error..........................................................................19
Clock Requirements...................................................................20
Connecting to the DSP...............................................................20
Outline Dimensions........................................................................21
Ordering Guide...........................................................................21
REVISION HISTORY
Revision 0: Initial Version
AD2S1200–SPECIFICATIONS
Table 1. (AVDD = DVDD = 5.0 V ± 5% @ −40°C to +125°C CLKIN 8.192 MHz, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DVDD
SAMPLE
RDVEL
SOE
DB11/SO
DB10/SCLK
DB9
DB8
DB7
RESET
FS2
FS1
LOT
DOS
DIR
CPO
DGND
DB6
DB5
DB4
DB3
DGND
DB2
DB1
DB0
XTA
CLKIN
FBY
AGND
Cos
Cos
SinLO
Sin
AGND
EXC
EXCFigure 2. Pin Configuration
44-Lead Low Profile Quad Flat Package [LQFP] (ST-44)
Table 3. Pin Function Descriptions RESOLVER FORMAT SIGNALS Vr = Vp× Sin(ϖt)
Vb = Vs× Sin(ϖt)× Sin(θ)
(A) CLASSICAL RESOLVERS3
Va = Vs× Sin(ϖt)× Cos(θ)
Vr = Vp× Sin(ϖt)
Vb = Vs× Sin(ϖt)× Sin(θ)
(B) VARIABLE RELUCTANCE RESOLVERS3
Va = Vs× Sin(ϖt)× Cos(θ)
Figure 3. Classical Resolver vs. Variable Reluctance Resolver
A resolver is a rotating transformer typically with a primary
winding on the rotor and two secondary windings on the stator.
In the case of a variable reluctance resolver, there are no wind-
ings on the rotor as shown in Figure 3. The primary winding is
on the stator as well as the secondary windings, but the saliency
in the rotor design provides the sinusoidal variation in the
secondary coupling with the angular position. Either way, the
resolver output voltages (S3–S1, S2–S4) will have the same
equations as shown in Equation 1.
AmplitudeExcitationRotorE
FrequencyExcitationRotortSin
AngleShaft
CostSinESS
SinSinESS=−=−23ω
Equation 1.
The stator windings are displaced mechanically by 90° (see
Figure 3). The primary winding is excited with an ac reference.
The amplitude of subsequent coupling onto the stator secon-
dary windings is a function of the position of the rotor (shaft)
relative to the stator. The resolver, therefore, produces two
output voltages (S3–S1, S2–S4) modulated by the SinE and
CoSinE of shaft angle. Resolver format signals refer to the
signals derived from the output of a resolver as shown in
Equation 1. Figure 4 illustrates the output format.
S2 TO S4(Cos)
S3 TO S1(Sin)
R2 TO R4(REF)
90°180°
270°360°Figure 4. Electrical Resolver Representation
PRINCIPLE OF OPERATION The AD2S1200 operates on a Type II tracking closed-loop
principle. The output continually tracks the position of the
resolver without the need for external convert and wait states.
As the resolver moves through a position equivalent to the least
significant bit weighting, the output is updated by one LSB.
The converter tracks the shaft angle θ by producing an output
angle ϕ that is fed back and compared to the input angle θ, and
the resulting error between the two is driven towards 0 when
the converter is correctly tracking the input angle. To measure
the error, S3–S1 is multiplied by Cosϕ and S2–S4 is multiplied
by Sinϕ to give 21toSSinCostSinEtoSCosSintSinEθωθω
The difference is taken, giving (0θ−θ×ωSinCosCosSintSinE
Equation 2.
This signal is demodulated using the internally generated
synthetic reference, yielding (0φθφθSinCosCosSinE−
Equation 3.
Equation 3 is equivalent to E0 Sin (θ − ϕ), which is
approximately equal to E0 (θ − ϕ) for small values of θ − ϕ,
where θ − ϕ = angular error.
The value E0 (θ − ϕ) is the difference between the angular error
of the rotor and the converter’s digital angle output.
A phase-sensitive demodulator, integrators, and a compensation
filter form a closed-loop system that seeks to null the error
signal. When this is accomplished, ϕ equals the resolver angle θ
within the rated accuracy of the converter. A Type II tracking
loop is used so that constant velocity inputs can be tracked
without inherent error.
For more information about the operation of the converter, see
the Circuit Dynamics section.
FAULT DETECTION CIRCUIT The AD2S1200 fault detection circuit will detect loss of resolver
signals, out of range input signals, input signal mismatch, or loss
of position tracking. In these cases, the position indicated by the
AD2S1200 may differ significantly from the actual shaft
position of the resolver.
Monitor Signal The AD2S1200 generates a monitor signal by comparing the
angle in the position register to the incoming Sin and Cos
signals from the resolver. The monitor signal is created in a
similar fashion to the error signal described in the Principle of
Operation section. The incoming signals Sinθ and Cosθ are
multiplied by the Sin and Cos of the output angle, respectively,
and then added together as shown below: ×+θCosASinxSinAMonitor21
Equation 4.
Where A1 is the amplitude of the incoming Sin signal (A1 ×
Sinθ), A2 is the amplitude of the incoming Cos signal (A2 ×
Cosθ), θ is the resolver angle, and ϕ is the angle stored in the
position register. Note that Equation 4 is shown after demodula-
tion, with the carrier signal Sinωt removed. Also note that for
matched input signal (i.e., no-fault condition), A1 = A2.
When A1 = A2 and the converter is tracking (θ = ϕ), the
monitor signal output has a constant magnitude of A1 (Monitor
= A1 × (Sin2 θ + Cos2 θ) = A1), independent of shaft angle.
When A1 ≠ A2, the monitor signal magnitude varies between
A1 and A2 at twice the rate of shaft rotation. The monitor signal
is used as described in the following sections to detect
degradation or loss of input signals.
Loss of Signal Detection Loss of signal (LOS) is detected when either resolver input (Sin
or Cos) falls below the specified LOS Sin/Cos threshold by
comparing the monitor signal to a fixed minimum value. LOS is
indicated by both DOS and LOT latching as logic low outputs.
The DOS and LOT pins are reset to the no fault state by a rising
edge of SAMPLE. The LOS condition has priority over both the
DOS and LOT conditions, as shown in Table 4. LOS is indicated
within 45° of angular output error worst case.
Signal Degradation Detection Degradation of signal (DOS) is detected when either resolver
input (Sin or Cos) exceeds the specified DOS Sin/Cos threshold
by comparing the monitor signal to a fixed maximum value.
DOS is also detected when the amplitude of the input signals
Sin and Cos mismatch by more than the specified DOS Sin/
Cos mismatch by continuously storing the minimum and
maximum magnitude of the monitor signal in internal registers,
and calculating the difference between the minimum and
maximum. DOS is indicated by a logic low on the DOS pin, and
is not latched when the input signals exceed the maximum
input level. When DOS is indicated due to mismatched signals,
the output is latched low until a rising edge of SAMPLE resets
the stored minimum and maximum values. The DOS condition
has priority over the LOT condition, as shown in Table 4. DOS
is indicated within 30° of angular output error worst case.
Loss of Position Tracking Detection Loss of tracking (LOT) is detected for three separate conditions: When the internal error signal of the AD2S1200 has
exceeded 5° When the input signal exceeds the maximum tracking rate
of 60,000 rpm (1,000 rps) When the internal position (at the position integrator)
differs from the external position (at the position register)
by more than 5°
LOT is indicated by a logic low on the LOT pin, and is not
latched. LOT has a 4° hysteresis, and is not cleared until the
internal error signal or internal/external position mismatch is
less than 1°. When the maximum tracking rate is exceeded, LOT
is cleared when both the velocity is less than 1,000 rps and the
internal/external position mismatch is less than 1°. LOT can be
indicated for step changes in position (such as after a RESET
signal is applied to the AD2S1200), or for accelerations
>~85,000 rps2. LOT is useful as a built-in test (BIT) that the
tracking converter is functioning properly. The LOT condition
has lower priority than both the DOS and LOS conditions as
shown in Table 4. The LOT and DOS conditions cannot be
indicated at the same time.
Table 4. Fault Detection Decoding
Condition Loss of Signal 0 0
Responding to a Fault Condition If any fault condition (LOS, DOS, or LOT) is indicated by the
AD2S1200, the output data must be presumed to be invalid.
This means that even if a RESET or SAMPLE pulse releases the
fault condition, the output data may be corrupted, even though
a fault may not be immediately indicated after the RESET/
SAMPLE event. As discussed earlier, there are some fault
conditions with inherent latency. If the device fault is cleared,
there could be some latency in the resolver’s mechanical
position before the fault condition is re-indicated.
When a fault is indicated, all output pins will still provide data,
although the data may or may not be valid. The fault condition
will not force the parallel, serial, or encoder outputs to a known
state. However, a new startup sequence is recommended only
after a LOS fault has been indicated.
Response to specific fault conditions is a system-level
requirement. The fault outputs of the AD2S1200 indicate that
the device has sensed a potential problem with either the
internal or external signals of the AD2S1200. It is the
responsibility of the system designer to implement the
appropriate fault-handling schemes within the control hardware
and/or algorithm of a given application based on the indicated
fault(s) and the velocity or position data provided by the
AD2S1200.
False Null Condition Resolver-to-digital converters that employ Type II tracking
loops based on the error equation (Equation 3) presented in the
Principle of Operation section can suffer from a condition
known as “false null.” This condition is caused by a metastable
solution to the error equation when θ − ϕ = 180°. The
AD2S1200 is not susceptible to this condition because its
hysteresis is implemented externally to the tracking loop.
Because of the loop architecture chosen for the AD2S1200, the
internal error signal always has some movement (1 LSB per
clock cycle), and so, in a metastable state, the converter will
always move to an unstable condition within one clock cycle,
causing the tracking loop to respond to the false null condition
as if it were a 180° step change in input position (the response
time is the same as specified in Dynamic Performance section
of Table 1). Therefore, it is impossible to enter the metastable
condition any time after the startup sequence as long as the
resolver signals are valid. However, in a case of a loss of signal, a
full reset is recommended to avoid the possibility of a false null
condition. The response to the false null condition has been
included in the value of tTRACK provided in the Supply
Sequencing and Reset section.
CONNECTING THE CONVERTER Refer to Figure 5. Ground should be connected to the AGND
pin and DGND pin. Positive power supply VDD = +5 V dc ± 5%
should be connected to the AVDD pin and DVDD pin. Typical
values for the decoupling capacitors are 10 nF and 4.7 µF,
respectively. These capacitors should be placed as close to the
device pins as possible, and should be connected to both AVDD
and DVDD. If desired, the reference oscillator frequency can be
changed from the nominal value of 10 kHz using FS1 and FS2.
Typical values for the oscillator decoupling capacitors are 20 pF.
Typical values for the reference decoupling capacitors are 10 µF
and 0.01 µF, respectively.
04406-0-005
5V
RESET
20pF20pF
4.7µF10nF
10µFFigure 5. Connecting the AD2S1200 to a Resolver
The gain of the buffer depends on the type of resolver used.
Since the specified excitation output amplitudes are matched to
the specified Sin/Cos input amplitudes, the gain of the buffer is
determined by the attenuation of the resolver.
In this recommended configuration, the converter introduces a
VREF/2 offset in the Sin, Cos signals coming from the resolver.
Of course, the SinLO and CosLO signals may be connected to a
different potential relative to ground, as long as the Sin and Cos
signals respect the recommended specifications. Note that since
the EXC/EXC outputs are differential, there is an inherent gain
of 2×.
For example, if the primary to secondary turns ratio is 2:1, the
buffer will have unity gain. Likewise, if the turns ratio is 5:1, the
gain of the buffer should be 2.5×. Figure 6 suggests a buffer
circuit. The gain of the circuit is 1/2(RRGain−=
and×−+×=INREFOUTVRVV11
VREF is set so that VOUT is always a positive value, eliminating the
need for a negative supply.
EXC/EXC(VIN)
Figure 6. Buffer Circuit
Separate screened twisted cable pairs are recommended for
analog inputs Sin/SinLO and Cos/CosLO. The screens should
terminate to REFOUT. To achieve the dynamic performance
specified, an 8.192 MHz crystal must be used.
ABSOLUTE POSITION AND VELOCITY OUTPUT The angular position and angular velocity are represented by
binary data and can be extracted either via a 12-bit parallel
interface or a 3-wire serial interface that operates at clock rates
up to 25 MHz. The chip select pin, CS, must be held low to
enable the device. Angular position and velocity can be selected
using a dedicated polarity input, RDVEL.
SOE Input The serial output enable pin, SOE, is held high to enable the
parallel interface. The SOE pin is held low to enable the serial
interface, which places pins (DB0–DB9) in the high impedance
state, while DB11 is the serial output (SO), and DB10 is the
serial clock input (SCLK).
Data Format The digital angle signal represents the absolute position of the
resolver shaft as a 12-bit unsigned binary word. The digital
velocity signal is a 12-bit twos complement word, which
represents the velocity of the resolver shaft rotating in either a
clockwise or a counterclockwise direction.
Finally, the RD input is used to read the data from the output
register and to enable the output buffer. The timing
requirements for the read cycle are illustrated in Figure 7.
SAMPLE Input Data is transferred from the position and velocity integrators
respectively to the position and velocity registers following a
high to low transition of the SAMPLE signal. This pin must be
held low for at least t1 ns to guarantee correct latching of the
data. RD should not be pulled low before this time. Also, a
rising edge of SAMPLE resets the internal registers that contain
the minimum and maximum magnitude of the monitor signal.
PARALLEL INTERFACE The angular position and angular velocity are available on the
AD2S1200 in two 12-bit registers, which can be accessed via the
12-bit parallel port. The parallel interface is selected holding the
SOE pin high. Data is transferred from the velocity and position
integrators, respectively, to the position and velocity registers
following a high-to-low transition on the SAMPLE pin. The
RDVEL polarity pin selects which register from the position or
the velocity registers is transferred to the output register. The CS
pin must be held low to transfer the selected data register to the
output register. Finally, the RD input is used to read the data
from the output register and to enable the output buffer. The
timing requirements for the read cycle are shown in Figure 7.
SAMPLE Input Data is transferred from the position and velocity integrators,
respectively, to the position and velocity registers following a
high-to-low transition on the SAMPLE signal. This pin must be
held low for at least t1 ns to guarantee correct latching of the
data. RD should not be pulled low before this time since data
would not be ready. The converter will continue to operate
during the read process. Also, a rising edge of SAMPLE resets
the internal registers that contain the minimum and maximum
magnitude of the monitor signal.
CS Input The device will be enabled when CS is held low.
RDVEL Input RDVEL input is used to select between the angular position and
velocity registers as shown in Figure 7. RDVEL is held high for
angular position and low for angular velocity. The RDVEL pin
must be set (stable) at least t4 ns before the RD pin is pulled low.
RD Input The 12-bit data bus lines are normally in a high impedance
state. The output buffer is enabled when CS and RD are held
low. A falling edge of the RD signal transfers data to the output
buffer. The selected data is made available to the bus to be read
within t6 ns of the RD pin going low. The data pins will return to
high impedance state when the RD returns to high state, within
t7 ns. If the user is reading data continuously, RD can be
reapplied a minimum of t5 ns after it was released.
