AD28MSP02BR ,Voiceband Signal Portspecifications.The output of the interpolation filter is fed to the DAC’s digitalSCLK O/Z Serial cl ..
AD28MSP02KN ,Voiceband Signal PortCharacteristics.” Refer to “Analog Input” inThe inclusion of on-chip anti-aliasing and anti-imaging ..
AD28MSP02KR ,Voiceband Signal Portcharacteristics of the filter, for example using a digital filter design softwareFigure 3 shows the ..
AD2S100AP ,AC Vector ProcessorGENERAL DESCRIPTIONstatus of the AD2S100. The busy period represents the conver-The AD2S100 perform ..
AD2S105AP ,Three-Phase Current ConditionerGENERAL DESCRIPTION2The AD2S105 performs the vector rotation of three-phase 120 The AD2S105 is fabr ..
AD2S1200WST ,12-Bit R/D Converter with Reference OscillatorAPPLICATIONS binary position data accessed either via a 12-bit parallel Electric power steering por ..
AD8534AR ,Low Cost, 250 mA Output Single-Supply AmplifiersGENERAL DESCRIPTION+IN A 3 6 –IN B+IN A 3 6 –IN BThe AD8531, AD8532 and AD8534 are single, dual and ..
AD8534ARU ,Low Cost, 250 mA Output Single-Supply AmplifiersCHARACTERISTICSOffset Voltage V 25 mVOS £ +85
AD28MSP02BR-AD28MSP02KN-AD28MSP02KR
Voiceband Signal Port
FUNCTIONAL BLOCK DIAGRAMREV.0
Voiceband Signal Port
FEATURES
Complete Analog I/O Port for Voiceband DSP
Applications
Linear-Coded 16-Bit Sigma-Delta ADC
Linear-Coded 16-Bit Sigma-Delta DAC
On-Chip Anti-Aliasing and Anti-lmaging Filters
On-Chip Voltage Reference
8 kHz Sampling Frequency
Twos Complement Coding
65 dB SNR + THD
Programmable Gain on DAC and ADC
Serial Interface To DSP Processors
24-Pin DlP/28-Lead SOIC
Single 5 V Power Supply
GENERAL DESCRIPTIONThe AD28msp02 Voiceband Signal Port is a complete analog
front end for high performance voiceband DSP applications.
Compared to traditional μ-law and A-law codecs, the
AD28msp02’s linear-coded ADC and DAC maintain wide
dynamic range while maintaining superior SNR and THD. A
sampling rate of 8.0 kHz coupled with 65 dB SNR + THD per-
formance make the AD28msp02 attractive in many telecom and
speech processing applications, for example digital cellular radio
and high quality telephones. The AD28msp02 simplifies overall
system design by requiring only a single +5 V power supply.
The inclusion of on-chip anti-aliasing and anti-imaging filters,
16-bit sigma-delta ADC and DAC, and programmable gain
amplifiers ensures a highly integrated and compact solution to
voiceband analog processing requirements. Sigma-delta conver-
sion technology eliminates the need for complex off-chip anti-
aliasing filters and sample-and-hold circuitry.
The AD28msp02’s serial I/O port provides an easy interface to
host DSP microprocessors such as the ADSP-2101, ADSP-2105
and ADSP-2111. The AD28msp02 is available in a 24-pin, 0.3"
plastic DIP and a 28-lead SOIC package.
FUNCTIONAL DESCRIPTIONFigure 1 shows a block diagram of the AD28msp02.
A/D CONVERSIONThe A/D conversion circuitry of the AD28msp02 consists of two
analog input amplifiers, an optional 20 dB preamplifier, and
a sigma-delta analog-to-digital converter (ADC). The analog
input signal to the AD28msp02 must be ac-coupled.
Analog Input AmplifiersThe two analog input amplifiers (NORM, AUX) are internally
biased by an on-chip voltage reference in order to allow opera-
tion of the AD28msp02 with a single +5 V power supply.
An analog multiplexer selects either the NORM or AUX ampli-
fier as the input to the ADC’s sigma-delta modulator. The
optional 20 dB preamplifier may be used to increase the signal
level; the preamplifier can be inserted before the modulator or
can be bypassed. Input signal level to the sigma-delta modulator
should not exceed VINMAX, which is specified under “Analog
Interface Electrical Characteristics.” Refer to “Analog Input” in
the “Design Considerations” section of this data sheet for more
information.
The input multiplexer and 20 dB preamplifier are configured by
Bits 0 and 1 (IPS, IMS) of the AD28msp02’s control register. If
the multiplexer setting is changed while an input signal is being
processed, the ADC’s output must be allowed time to settle to
ensure that the output data is valid.
ADCThe ADC consists of a 2nd-order analog sigma-delta modulator,
an anti-aliasing decimation filter, and a digital high-pass filter.
The sigma-delta modulator noise-shapes the signal and pro-
duces 1-bit samples at a 1.0 MHz rate. This bit stream, which
represents the analog input signal, is fed to the anti-aliasing
decimation filter.
Decimation FilterThe anti-aliasing decimation filter contains two stages. The first
stage is a sinc4 digital filter that increases resolution to 16 bits
and reduces the sample rate to 40 kHz. The second stage is an
IIR low-pass filter.
AD28msp02
OUTPUT
DIFFERENTIAL
AMP
VFBNORM
VINNORM
SDI
SDIFS
SDO
SDOFS
SCLK
DATA/
CNTRL
VFBAUX
VINAUX
VREF
VOUTP
VOUTNFigure 1.AD28msp02 Block Diagram
The IIR low-pass filter is a 10th-order elliptic filter with a pass-
band edge at 3.7 kHz and a stopband attenuation of 65 dB at
4 kHz. This filter has the following specifications:
Filter type:10th-order low-pass elliptic IIR
Sample frequency:40.0 kHz
Passband cutoff:*3.70 kHz
Passband ripple:±0.2 dB
Stopband cutoff:4.0 kHz
Stopband ripple:–65.00 dB
*The passband cutoff frequency is defined to be the last point in the passband
that meets the passband ripple specification.
(Note that these specifications apply only to this filter, and not to the entire
ADC. The specifications can be used to perform further analysis of the exact
characteristics of the filter, for example using a digital filter design software
package.)
Figure 2 shows the frequency response of the IIR low-pass filter.
FREQUENCY – Hz
LOG MAGNITUDE – dBFigure 2.IIR Low-Pass Filter Frequency Response
High-Pass FilterThe digital high-pass filter removes frequency components at
the low end of the spectrum; it attenuates signal energy below
the passband of the converter. The high-pass filter can be
The high-pass filter is a 4th-order elliptic filter with a passband
cutoff at 150 Hz. Stopband attenuation is 25 dB. This filter has
the following specifications:
Filter type:4th-order high-pass elliptic IIR
Sample frequency:8.0 kHz
Passband cutoff:150.0 Hz
Passband ripple:±0.2 dB
Stopband cutoff:100.0 Hz
Stopband ripple:–25.00 dB
(Note that these specifications apply only to this filter, and not to the entire
ADC. The specifications can be used to perform further analysis of the exact
characteristics of the filter, for example using a digital filter design software
package.)
Figure 3 shows the frequency response of the high-pass filter.
FREQUENCY – Hz
LOG MAGNITUDE – dBFigure 3.High-Pass Filter Frequency Response
Passband ripple is ±0.2 dB for the combined effects of the
ADC’s digital filters (i.e., high-pass filter and IIR low-pass of
the decimation filter) in the 300 Hz–3400 Hz passband.
The output of the ADC is transferred to the AD28msp02’s
serial port (SPORT) at an 8 kHz rate, for transmission to the
host DSP processor. Maximum group delay in the ADC will not
D/A CONVERSIONThe D/A conversion circuitry of the AD28msp02 consists of a
sigma-delta digital-to-analog converter (DAC), an analog
smoothing filter, a programmable gain amplifier, and a differen-
tial output amplifier.
DACThe AD28msp02’s sigma-delta DAC implements digital filters
and a sigma-delta modulator with the same characteristics as the
filters and modulator of the ADC. The DAC consists of a digital
high-pass filter, an anti-imaging interpolation filter, and a digital
sigma-delta modulator.
The DAC receives 16-bit samples from the host DSP processor
via AD28msp02’s serial port at an 8 kHz rate. If the host pro-
cessor fails to write a new value to the serial port, the existing
(previous) data is read again. The data stream is filtered first by
the DAC’s high-pass filter and then by the anti-imaging interpo-
lation filter. These filters have the same characteristics as the
ADC’s anti-aliasing decimation filter and digital high-pass filter.
The output of the interpolation filter is fed to the DAC’s digital
sigma-delta modulator, which converts the 16-bit data to 1-bit
samples at a 1.0 MHz rate. The modulator noise-shapes the sig-
nal such that errors inherent to the process are minimized in the
passband of the converter. The bit stream output of the sigma-
delta modulator is fed to the AD28msp02’s analog smoothing
filter where it is converted to an analog voltage.
High-Pass FilterThe digital high-pass filter of the AD28msp02’s DAC has the
same characteristics as the high-pass filter of the ADC. The
high-pass filter removes frequency components at the low end of
the spectrum; it attenuates signal energy below the passband of
the converter. The DAC’s high-pass filter can be bypassed by
setting the DABY bit (Bit 2) of the AD28msp02’s control
register.
The high-pass filter is a 4th-order elliptic filter with a passband
cutoff at 150 Hz. Stopband attenuation is 25 dB. This filter has
the following specifications:
Filter type:4th-order high-pass elliptic IIR
Sample frequency:8.0 kHz
Passband cutoff:150.0 Hz
Passband ripple:±0.2 dB
Stopband cutoff:100.0 Hz
Stopband ripple:–25.00 dB
(Note that these specifications apply only to this filter, and not to the entire DAC.
The specifications can be used to perform further analysis of the exact characteris-
tics of the filter, for example using a digital filter design software package.)
Figure 3 shows the frequency response of the high-pass filter.
Interpolation FilterThe anti-imaging interpolation filter contains two stages. The
first stage is an IIR low-pass filter that interpolates the data rate
from 8 kHz to 40 kHz and removes images produced by the in-
terpolation process. The output of this stage is then interpolated
to 1.0 MHz and fed to the second stage, a sinc4 digital filter that
attenuates images produced by the 40 kHz to 1.0 MHz inter-
polation process.
PIN DESCRIPTIONS
Pin NameI/O/Z FunctionVINNORMIAnalog input to inverting terminal of
NORM input amplifier.
VFBNORMOOutput terminal of NORM amplifier.
VINAUXIAnalog input to inverting terminal of
AUX input amplifier.
VFBAUXOOutput terminal of AUX amplifier.
VOUTPOAnalog output from noninverting
terminal of differential output amplifier.
VOUTNOAnalog output from inverting terminal of
differential output amplifier.
VREFOOn-chip bandgap voltage reference
(2.5 V ± 10%).
MCLKIMaster clock input; frequency must
equal 13.0 MHz to guarantee listed
specifications.
SCLKO/ZSerial clock used to clock data or control
bits to and from the serial port
(SPORT). The frequency of SCLK is
equal to the frequency of the master
clock (MCLK) divided by 5. SCLK is
3-stated when CS is low.
SDIISerial data input of SPORT. Both data
and control information are input on
this pin. Input at SDI is ignored when
CS is low.
SDOO/Z Serial data output of SPORT. Both data
and control information are output on
this pin. SDO is 3-stated when CS is
low.
SDIFSIFraming signal for SDI serial transfers.
Input at SDIFS is ignored when CS is
low.
SDOFSO/ZFraming signal for SDO serial transfers.
SDOFS is 3-stated when CS is low.
DATA/CNTRLIConfigures AD28msp02 for either data
or control information transfers (via
SPORT).IActive-high chip select. Can be used to
3-state the SPORT interface; when CS
is low, the SCLK, SDO, and SDOFS
outputs are 3-stated and the SDI and
SDIFS inputs are ignored. If CS is de-
asserted during a serial data transfer, the
16-bit word being transmitted is lost.
RESETIActive low reset signal; resets Control
Register and clears digital filters. RESET
does not 3-state the SPORT outputs
(SCLK, SDO, SDOFS).
VCCAnalog supply voltage; nominal +5 V.
GNDAAnalog ground.
VDDDigital supply voltage; nominal +5 V.
GNDDDigital ground.
AD28msp02The IIR low-pass filter is a 10th-order elliptic filter with a pass-
band edge at 3.70 kHz and a stopband attenuation of 65 dB at
4 kHz. This filter has the following specifications:
Filter type:l0th-order low-pass elliptic IIR
Sample frequency:40.0 kHz
Passband cutoff:*3.70 kHz
Passband ripple:±0.2 dB
Stopband cutoff:4.0 kHz
Stopband ripple:–65.00 dB
*The passband cutoff frequency is defined to be the last point in the passband
that meets the passband ripple specification.
(Note that these specifications apply only to this filter, and not to the entire
DAC. The specifications can be used to perform further analysis of the exact
characteristics of the filter, for example using a digital filter design software
package.)
Figure 2 shows the frequency response of the IIR low-pass filter.
Passband ripple is ±0.2 dB for the combined effects of the
DAC’s digital filters (i.e., high-pass filter and IIR low pass of the
interpolation filter) in the 300 Hz–3400 Hz passband.
Analog Smoothing Filter and Programmable Gain AmplifierThe programmable gain amplifier (PGA) can be used to adjust
the output signal level by –15 dB to +6 dB. This gain is selected
by bits 7–9 (OG0, OG1, OG2) of the AD28msp02’s control
register.
The AD28msp02’s analog smoothing filter consists of a 2nd-
order Sallen-Key continuous-time filter and a 3rd-order
switched capacitor filter. The Sallen-Key filter has a 3 dB point
at approximately 80 kHz.
Differential Output AmplifierThe AD28msp02’s analog output (VOUTP, VOUTN) is pro-
duced by a differential output amplifier. The differential ampli-
fier can drive loads of 2 kΩ or greater and has a maximum
differential output voltage swing of ±3.156 V peak-to-peak
(3.17 dBm0). The output signal is dc-biased to the
AD28msp02’s on-chip voltage reference (VREF) and can be
ac-coupled directly to a load or dc-coupled to an external ampli-
fier. Refer to “Analog Output” in the “Design Considerations”
section of this data sheet for more information.
The VOUTP–VOUTN outputs must be used as differential out-
puts; do not use either as a single-ended output.
SERIAL PORTThe AD28msp02 communicates with a host processor via the
bidirectional synchronous serial port (SPORT). The SPORT is
used to transmit and receive digital data and control information.
All serial transfers are 16 bits long, MSB first. Data bits are
transferred at the serial clock rate (SCLK). SCLK equals the
master clock frequency divided by 5. SCLK = 2.6 MHz for the
master clock frequency MCLK = 13.0 MHz.
Host Processor InterfaceThe AD28msp02-to-host processor interface is shown in Figure 4.
Figure 4.AD28msp02-to-Host Processor Interface
Table I describes the SPORT signals and how they are used to
communicate with the host processor. The AD28msp02’s chip
select (CS) must be held high to enable SPORT operation. CS
can be used to 3-state the SPORT pins and disable communica-
tion with the host processor.
To use the ADSP-2101 or ADSP-2111 as host DSP processor
for the AD28msp02, the following connections can be used (as
shown in Figure 5):
Table I.SPORT Signals(CS must be held high to enable SPORT operation.)
*Outputs last data value that was valid prior to entering powerdown.
Note that the ADSP-2101’s SPORT0 communicates with the
AD28msp02’s SPORT while the ADSP-2101’s Flag Output
(FO) is used to signal the AD28msp02’s DATA/CNTRL input.
SPORT1 on the ADSP-2101 must be configured for flags and
interrupts in this system.
Figure 6 shows an ADSP-2101 assembly language program that
initializes the AD28msp02 and implements digital loopback
through the DSP processor.
Figure 5.AD28msp02-to-ADSP-2101 Interface
Figure 6.ADSP-2101 Digital Loopback Routine
AD28msp02Gain settings are accurate within ±0.6 dB.
(Control Register is set to 0x0000 at RESET. Reserved Bits
Table II.Control Word Write Format14131211109876543210
Serial Data OutputThe AD28msp02’s SPORT will begin transmitting data to the
host processor at an 8 kHz rate when the PWDD and PWDA
bits (Bits 4, 5) of the control register are set to 1. In the pro-
gram shown in Figure 6, the instructions
AX0 = 0x30; { Write control word to take }
TX0 = AX0; { AD28msp02 out of powerdown }
accomplish this by writing 0x30 to the AD28msp02’s control
register. There is a short start-up time (after the end of this con-
trol register write) before the AD28msp02 raises SDOFS and
begins transmitting data; see Figure 11.
At the 13 MHz MCLK frequency, data is transmitted at an
8 kHz rate with a single 16-bit word transmitted every 125 μs.
While data is being output, the AD28msp02 asserts SDOFS at
an 8 kHz rate. Each 16-bit word transfer begins one serial clock
cycle after SDOFS is asserted.
Serial Data InputThe host processor must initiate data transfers to the
AD28msp02 by asserting the serial data input frame sync
(SDIFS) high. The 16-bit word transfer begins one serial clock
cycle after SDIFS is asserted. The DATA/CNTRL line must be
driven high when SDIFS is driven high.
The host processor must assert SDIFS shortly after the rising
edge of SCLK and must maintain SDIFS high for one cycle.
Data is then driven from the host processor (to the SDI input)
shortly after the rising edge of the next SCLK and is clocked
into the AD28msp02 on the falling edge of SCLK in that cycle.
Each bit of a 16-bit data word is thus clocked into the
AD28msp02 on the falling edge of SCLK (MSB first).
If SDIFS is asserted high again before the end of the present
data word transfer, it is not recognized until the falling edge of
SCLK in the last (LSB) cycle.
(Note: Exact SPORT timing requirements are defined in the
“Specifications” section of this data sheet.)
CONTROL REGISTERThe AD28msp02’s control register configures the device for
various modes of operation including ADC and DAC gain set-
tings, ADC input mux selection, filter bypass, and powerdown.
The AD28msp02’s host processor can read and write to the
control register through the AD28msp02’s serial port (SPORT)
by driving the DATA/CNTRL pin low.
The control register is cleared (set to 0x0000) when the
AD28msp02 is reset.
Control Register WritesTo write the control register, the host processor must assert
DATA/CNTRL low when it asserts SDIFS. If the MSB of
the bit stream is also low, the SPORT recognizes the incoming
serial data as a new control word and copies it to the
AD28msp02’s control register. The format for the control word
write is shown in Table II; reserved Bits 10-15 must be set to
zero.IPSAnalog input preamplifier select: 1 = insert (+20 dB), 0 = bypass (0 dB)IMSAnalog input multiplexer select: 1 = AUX input, 0 = NORM inputDABYDAC high-pass filter bypass select: 0 = insert, 1 = bypassADBYADC high-pass filter bypass select: 0 = insert, 1 = bypassPWDAPowerdown analog: 0 = powerdown, 1 = operatingPWDDPowerdown digital: 0 = powerdown, 1 = operating
7–9OG2-OG0Analog output gain setting (for D/A output PGA)
10–15Reserved
Table III. Control Word Read Format
Read Request14131211109876543210
Read Ready14131211109876543210
Control Register ReadsTo read the control register, the host processor must transfer
two control words. For each transfer, the DATA/CNTRL pin
must be low when SDIFS is asserted. If the MSB of the bit
stream is high, the SPORT recognizes the incoming serial data
as a request for control information. The protocol for reading
the control register is as follows:The host processor sends a “Read Request” control word to
the AD28msp02. Since the MSB of this control word is high,
the SPORT recognized the incoming serial data as a read re-
quest and does not overwrite the control register.When the AD28msp02 receives the read request, it finishes
any data transfers in progress and waits for a “Read Ready”
control word.The host processor then transfers a “Read Ready” control
word to the AD28msp02. Upon receiving this control word,
the AD28msp02 transfers the control register contents to the
host processor via the SPORT.When the SPORT completes the control register transfer, it
immediately resumes transmitting data at an 8 kHz rate.
This scheme allows any data transfers in progress to be com-
pleted and resolves any ambiguities between data and control
words. The format for the read control words is shown in
Table III.
DESIGN CONSIDERATIONS
Analog InputThe analog input signal to the AD28msp02 must be ac-coupled.
Figure 7 shows the recommended input circuit for the
AD28msp02’s analog input pin (either VINNORM or VINAUX).
The circuit of Figure 7 implements a first-order low-pass filter
with a 3 dB point at 20 kHz; this is the only filter that must be
implemented external to the AD28msp02 to prevent aliasing of
the sampled signal. Since the AD28msp02’s ADC uses a highly
oversampled approach that transfers the bulk of the anti-aliasing
filtering into the digital domain, the off-chip anti-aliasing filter
need only be of low order.
In the circuit shown in Figure 7, scaling of the analog input is
achieved by the resistors RIN and RFB. The input signal gain,
–RFB/RIN, can be adjusted from –12 dB to +26 dB by varying
the values of these resistors. The AD28msp02’s on-chip 20 dB
preamplifier can be enabled when there is not enough gain in
the input circuit; the preamplifier is configured by Bit 0 (IPS) of
the control register. Total gain must be configured to ensure
that a full-scale input signal (at CIN in Figure 7) produces a sig-
nal level at the input to the sigma-delta modulator of the ADC
that does not exceed VINMAX, which is specified under “Analog
Interface Electrical Characteristics.” If the total gain is increased
above unity, signal-to-noise (SNR + THD) performance will
not meet the listed specifications.
Figure 7.Recommended Analog Input Circuit
The dc biasing of the analog input signal is accomplished with
an on-chip voltage reference which nominally equals 2.5 V. The
input signal must be ac-coupled with an external coupling ca-
pacitor (CIN). CIN and RIN should be chosen to ensure a cou-
pling corner frequency of 30 Hz. CIN should be 0.1 μF or larger.
AD28msp02To select values for the components shown in Figure 7, use the
following equations:
Gain=RFBIN IN=1πRIN FB=1π)(20×103)RFB
10 kΩ ≤ RFB, RIN ≤ 50 kΩ
150 pF ≤ CFB ≤ 600 pF
Figure 8 shows an example of a typical input circuit configured
for 0 dB gain. The circuit’s diodes are used to prevent the input
signal from exceeding maximum limits.
1.0µF
330pF
INPUT
SIGNAL
VCC
GNDA10kΩFigure 8.Example Analog Input Circuit for 0 dB Gain
Analog OutputThe AD28msp02’s differential analog output (VOUTP, VOUTN)
is produced by an on-chip differential amplifier. The differential
amplifier can drive a minimum load of 2 kΩ (RL ≥ 2 kΩ) and
has a maximum differential output voltage swing of ±3.156 V
peak-to-peak (3.17 dBm0). The differential output can be
ac-coupled directly to a load or dc-coupled to an external
amplifier.
Figure 9 shows a simple circuit providing a differential output
with ac coupling. The capacitor of this circuit (COUT) is
optional; if used, its value can be chosen as follows: OUT=1
(60π)RL
Figure 9.Example Circuit for Differential Output
The VOUTP–VOUTN outputs must be used as differential out-
puts; do not use either as a single-ended output. Figure 10
shows an example circuit which can be used to convert the dif-
ferential output to a single-ended output. The circuit uses a
differential-to-single-ended amplifier, the Analog Devices
SSM2141.
Figure 10.
Serial Output Startup TimeThe AD28msp02 begins transmitting data to the host processor
after it is taken out of powerdown. To take the AD28msp02 out
of powerdown, the host processor writes a control word to the
AD28msp02.
The start-up time (from the start of this control word write)
before the AD28msp02 begins transmitting data is shown in
Figure 11.
PC Board Layout ConsiderationsSeparate analog and digital ground planes should be provided
for the AD28msp02 in order to ensure the characteristics of the
device’s ADC and DAC. The two ground planes should be con-
nected at a single point—this is often referred to as a “Star” or
“Mecca” grounding configuration. The point of connection may
be at the system power supply, at the PC board power connec-
tion, or at any other appropriate location. Because ground loops
increase susceptibility to EMF, multiple connections between
the analog and digital ground planes should be avoided.
The ground planes should be designed such that all noise-
sensitive areas are isolated from one another and critical signal
traces (such as digital clocks and analog signals) are as short as
possible.
Each +5 V digital supply pin, VDD, of the AD28msp02 (SOIC
Pins 20, 21) should be bypassed to ground with a 0.1 μF capaci-
tor. These capacitors should be low inductance, monolithic, ce-
ramic, and surface-mount. The capacitor leads and PC board
traces should be as short as possible to minimize inductive ef-
fects. In addition, a 10 μF capacitor should be connected be-
tween VDD and ground, near the PC board power connection.
MCLK FrequencyThe sigma-delta converters and digital filters of the AD28msp02
are specifically designed to operate at a master clock (MCLK)
frequency of 13.0 MHz. MCLK must equal 13.0 MHz to guar-
antee the filter characteristics and sample rate of the ADC and
DAC. The AD28msp02 is not tested or characterized at any
other clock frequency.
A low cost crystal with a different frequency, for example
12.288 MHz, can be used for the master clock input; in this
case, however, the AD28msp02 is not guaranteed to meet the
specifications listed in this data sheet.
SDO
FIRST DATA WORD
TRANSMITTED
FROM AD28msp02
SCLK
DATA/
CNTRL
SDIFS
SDOFS
SDI
POWERUP CONTROL WORDFigure 11.Serial Output Startup Time
AD28msp02
DEFINITION OF SPECIFICATIONS
Absolute GainAbsolute gain is a measure of converter gain for a known signal.
Absolute gain is measured with a 1.0 kHz sine wave at 0 dBm0.
The absolute gain specification is used as a reference for gain
tracking error specification.
Gain Tracking ErrorGain tracking error measures changes in converter output for
different signal levels relative to an absolute signal level. The ab-
solute signal level is 1 kHz at 0 dBm0 (equal to absolute gain).
Gain tracking error at 0 dBm0 is 0 dB by definition.
SNR + THDSignal-to-noise ratio plus total harmonic distortion is defined to
be the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components in the frequency range
300 Hz–3400 Hz, including harmonics but excluding dc.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m or n are equal to zero. For final testing, the second or-
der terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb).
Idle Channel NoiseIdle channel noise is defined as the total signal energy measured
at the output of the device when the input is grounded (mea-
sured in the frequency range 300 Hz–3400 Hz).
CrosstalkCrosstalk is defined as the ratio of the amplitude of a full-scale
signal appearing on one channel to the amplitude of the same
signal which couples onto the adjacent channel. Crosstalk is ex-
pressed in dB.
Power Supply RejectionPower supply rejection measures the susceptibility of a device to
noise on the power supply. Power supply rejection is measured
by modulating the power supply with a sine wave and measuring
the noise at the output (relative to 0 dB).
Group DelayGroup delay is defined as the derivative of radian phase with re-
spect to radian frequency, ∂φ(ω)/∂ω. Group delay is a measure
of average delay of a system as a function of frequency. A linear
system with a constant group delay has a linear phase response.
The deviation of group delay away from a constant indicates the
degree of nonlinear phase response of the system.
