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AD28MSP01KR ,PSTN Signal PortGENERAL DESCRIPTION On-chip bit and baud clock generation circuitry provides forThe AD28msp01 is a ..
AD28MSP02BN ,Voiceband Signal PortCharacteristics.” Refer to “Analog Input” inThe inclusion of on-chip anti-aliasing and anti-imaging ..
AD28MSP02BR ,Voiceband Signal Portspecifications.The output of the interpolation filter is fed to the DAC’s digitalSCLK O/Z Serial cl ..
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AD28MSP01
PSTN Signal Port
FUNCTIONAL BLOCK DIAGRAMREV.A
PSTN Signal Port
FEATURES
Complete Analog l/O Port for DSP-Based FAX/MODEM
Applications
Linear-Coded 16-Bit Sigma-Delta ADC
Linear-Coded 16-Bit Sigma-Delta DAC
On-Chip Anti-Alias and Anti-lmage Filters
Digital Resampling/lnterpolation Filter
7.2 kHz, 8.0 kHz, and 9.6 kHz Sampling Rates
8/7 Mode for 8.23 kHz, 9.14 kHz, and 10.97 kHz
Sampling Rates
Synchronous and Asynchronous DAC/ADC Modes
Bit and Baud Clock Generation
Transmit Digital Phase-Locked Loop for Terminal
Synchronization
Independent Transmit and Receive Phase Adjustment
Serial Interface to DSP Processors
+5 V Operation with Power-Down Mode
28-Pin Plastic DlP/44-Lead PLCC/28-Lead SOIC
APPLICATIONS
High Performance DSP-Based Modems
V.32ter, V.32bis, V.32, V.22bis, V.22, V.21,
Bell 212A, 103
Fax and Cellular-Compatible Modems
V.33, V.29, V.27ter, V.27bis, V.27, V.26bis
Integrated Fax, Modem, and Speech Processing
GENERAL DESCRIPTIONThe AD28msp01 is a complete analog front end for high perfor-
mance DSP-based modems. The device includes all data conver-
sion, filtering, and clock generation circuitry needed to imple-
ment an echo-cancelling modem with a single host digital signal
processor. Software-programmable sample rates and clocking
modes support all established modem standards. The AD28msp01
simplifies overall system design by requiring only +5 volts.
The inclusion of on-chip anti-aliasing and anti-imaging filters
and 16-bit sigma-delta ADC and DAC ensures a highly inte-
grated and compact solution for FAX or data MODEM applica-
tions. Sigma-delta conversion technology eliminates the need for
complex off-chip anti-aliasing filters and sample-and-hold circuitry.
The AD28msp01 utilizes advanced sigma-delta technology to
move the entire echo-cancelling modem implementation into the
digital domain. The device maintains a –72 dB SNR throughout
all filtering and data conversion. Purely DSP-based echo cancel-
lation algorithms can thereby maintain robust bit error rates
under worst-case signal attenuation and echo amplitude condi-
tions. The AD28msp01’s on-chip interpolation filter resamples
the received signal after echo cancellation in the DSP, freeing
the processor for other voice or data communications tasks.
On-chip bit and baud clock generation circuitry provides for
either synchronous or asynchronous operation of the transmit
(DAC) and receive (ADC) paths. Each path features indepen-
dent phase advance and retard adjustments via software control.
The AD28msp01 can also synchronize modem operation to an
external terminal bit clock.
The AD28msp01’s serial I/O port provides an easy interface to
host DSP microprocessors such as the ADSP-2101, ADSP-2105,
and ADSP-2111. Packaged in a 28-pin plastic DIP, 44-lead
PLCC, 44-pin TQFP, or 28-lead SOIC, the AD28msp01 pro-
vides a compact solution for space-constrained environments.
The device operates from a +5 V supply and offers a low power
sleep mode for battery-powered systems.
A detailed block diagram of the AD28msp01 is shown in
Figure 1.
AD28msp01Figure 1.AD28msp01 Block Diagram
PIN DESCRIPTIONS
NameTypeDescription
Analog InterfaceVINIAnalog input to the inverting terminal of the
input amplifier.
VFBOFeedback terminal of the input amplifier.
VOUTPOAnalog output from the noninverting terminal
of the output differential amplifier.
VOUTNOAnalog output from inverting terminal of the
output differential amplifier.
Serial InterfaceSCLKO/ZSerial clock used for clocking data or control
bits to/from the serial port (SPORT). The
frequency of this clock is 1.7280 MHz. This
pin is 3-stated when the CS is low.
SDIISerial data input of the SPORT. Both data
and control information are input on this pin.
This pin is ignored when CS is low.
SDOO/ZSerial data output of the SPORT. Both data
and control information are output on this
pin. This pin is 3-stated when CS is low.
SDIFSIFraming synchronization signal for serial data
transfers to the AD28msp01 (via the SDI
pin). This pin is ignored when CS is low.
NameTypeDescriptionSDOFSO/ZFraming synchronization signal for serial data
transfers from the AD28msp01 (via the SDO
pin). This pin is 3-stated when CS is low.
Clock GenerationTSYNCITransmit synchronization clock. This signal is
used to synchronize the transmit clocks and
the converter clocks to an external terminal/
bit-rate clock. It is used in the V.32 TSYNC
and Asynchronous TSYNC modes and is
ignored in other operating modes. The
frequency of the external clock must be
programmed in Control Register 0. This pin
must be tied high or low if it is not being
used.
TBITOTransmit bit rate clock. This is an output
clock whose frequency is programmable via
Control Register 3. It is synchronized with
the TCONV clock.
TBAUDOTransmit baud rate clock. This is an output
clock whose frequency is programmable via
Control Register 3. It is synchronized with
the TCONV clock.
PIN DESCRIPTIONS (Continued)
NameTypeDescriptionTCONVOTransmit conversion clock. This clock indicates
when the ADC has finished a sampling cycle.
The frequency of TCONV is programmed by
setting the sample rate field in Control Register
0. The programmed TCONV rate can be scaled
by a factor of 8/7 by setting Bit 9 in Control
Register 1. The phase of TCONV can be
adjusted by writing the Transmit Phase Adjust
Register (Control Register 5).
RBITOReceive bit rate clock. This is an output clock
whose frequency is programmable via Control
Register 2. It is synchronized with the RCONV
clock.
RBAUDOReceive baud rate clock. This is an output clock
whose frequency is programmable via Control
Register 2. It is synchronized with the RCONV
clock.
RCONVOReceive conversion clock. This clock indicates
when the DAC has finished a sampling cycle.
The frequency of RCONV is programmed by
setting the sample rate field in Control Register
0. The programmed RCONV rate can be scaled
by a factor of 8/7 by setting Bit 9 in Control
Register 1. The phase of RCONV can be
adjusted by writing the Receive Phase Adjust
Register (Control Register 4).
MiscellaneousMCLKIAD28msp01 master clock input. The frequency
of this clock must be 13.824 MHz to guarantee
listed specifications.
RESETIActive-low chip reset. This signal sets all
AD28msp01 control registers to their default
values and clears the device’s digital filters.
SPORT output pins are 3-stated when RESET
is low. SPORT input pins are ignored when
RESET is low.IActive-high chip select. This signal 3-states all
SPORT output pins and forces the AD28msp01
to ignore all SPORT input pins. If CS is
deasserted during a serial data transfer, the
16-bit word being transmitted is lost.
Power SuppliesVCCAnalog supply voltage (nominally +5 V)
GNDAAnalog ground
VDDDigital supply voltage (nominally +5 V)
GNDDDigital ground
FUNCTIONAL DESCRIPTION
A/D ConversionThe A/D conversion circuitry of the AD28msp01 consists of an
analog input amplifier and a sigma-delta analog-to-digital con-
verter (ADC). The analog input signal to the AD28msp01 must
be ac coupled.
Analog Input AmplifierThe analog input amplifier is internally biased by an on-chip
voltage reference in order to allow operation of the AD28msp01
with a +5 V power supply.
Input signal level to the sigma-delta modulator should not ex-
ceed VINMAX, which is specified under “Analog Interface Electri-
cal Characteristics.” Refer to “Analog Input” in the “Design
Considerations” section of this data sheet for more information.
ADCThe ADC consists of a 3rd-order analog sigma-delta modulator,
a decimation filter, an anti-aliasing low-pass filter, and a high-
pass filter. The analog input is applied to the input amplifier.
The output of this amplifier is applied to an analog sigma-delta
modulator which noise-shapes it and produces 1-bit samples at
a 1.7280 MHz rate. This bit stream is fed to the decimation
filter, which increases the resolution to 16-bits and decreases the
sampling frequency. The parallel data stream is then processed
by the anti-aliasing low-pass filter which further reduces the
sampling rate. Finally, the high-pass filter removes input fre-
quency components at the low end of the spectrum.
Either the high-pass filter alone or the high-pass/anti-aliasing
low-pass filter combination can be bypassed by setting the
appropriate bits in Control Register 1, thus producing samples
at 7.2/8.0/9.6 kHz or 28.8/32.0/38.4 kHz, respectively. The gain
and the frequency response of the AD28msp01 are altered when
these filters are bypassed. The DSP processor that receives
samples from the AD28msp01 may need to compensate for this
change.
Decimation FilterThe decimation filter is a sinc4 digital filter that increases resolu-
tion to 16 bits and reduces the sample rate to 28.8, 32.0, or
38.4 kHz (depending on the input sample rate). The 16 bit, par-
allel data stream output of the decimation filter is then pro-
cessed by the anti-aliasing low-pass filter.
Anti-Aliasing Low-Pass FilterThe anti-aliasing low-pass filter further reduces the sampling
rate by a factor of four to 7.2 kHz, 8.0 kHz, or 9.6 kHz (de-
pending on the output sample rate of the decimation filter). The
output is fed to the high-pass filter. The low-pass/high-pass filter
combination can be bypassed by setting the appropriate bits in
Control Register 1. If the filters are bypassed, the signal must be
scaled by the following multipliers to achieve normal levels:
2.046 for 9.6 kHz, 0.987 for 8.0 kHz, and 0.647 for 7.2 kHz.
When the filters are bypassed, the host DSP must be able to re-
ceive data at the 28.8/32.0/38.4 kHz rates. In this case,
resampling interpolation should be disabled because of insuffi-
cient bandwidth to transmit both ADC and resampled data to
the SPORT.
High-Pass Filter
AD28msp01The output of the ADC is transferred to the AD28msp01’s se-
rial port (SPORT) for transmission to the host DSP processor.
D/A CONVERSIONThe D/A conversion circuitry of the AD28msp01 consists of a
sigma-delta digital-to-analog converter (DAC) and a differential
output amplifier.
DACThe DAC consists of an anti-imaging low-pass filter, an interpo-
lation filter, a digital sigma-delta modulator, and an analog
smoothing filter. These filters have the same characteristics as
the ADC’s anti-aliasing filter and decimation filter.
The DAC receives 16-bit samples from the host DSP processor
via AD28msp01’s SPORT. If the host processor fails to write a
new value to the serial port, the existing (previous) data is read
again. The data stream is filtered first by the DAC’s anti-
imaging low-pass filter and then by the interpolation filter. The
output of the interpolation filter is fed to the DAC’s digital
sigma-delta modulator, which converts the 16-bit data to 1-bit
samples. The output of the sigma-delta modulator is fed to the
AD28msp01’s analog smoothing filter where it is converted into
a low-pass filtered, analog voltage.
Anti-lmaging Low-Pass FilterThe anti-imaging low-pass filter filters the 7.2 kHz, 8.0 kHz, or
9.6 kHz data stream form the SPORTs, and raises the sampling
rate to 28.8 kHz, 32.0 kHz, or 38.4 kHz.
The anti-imaging low-pass filter can be bypassed by setting the
appropriate bit in Control Register 1. This results in a gain
change. If the filter is bypassed, the signal must be scaled by the
following multipliers to achieve normal levels: 2.046 for 9.6 kHz,
0.987 for 8.0 kHz, and 0.647 for 7.2 kHz.
When the filter is bypassed, the host DSP must be able to trans-
mit data at the 28.8/32.0/38.4 kHz rates. In this case, re-
sampling interpolation should be disabled because of
insufficient bandwidth to transmit both ADC and resampled
data to the SPORT.
Interpolation FilterThe interpolation filter contains is a sinc4 digital filter which
raises the sampling rate to 1.7280 MHz by interpolating be-
tween the samples. These 16-bit samples are then processed by
the digital sigma-delta modulator which noise-shapes the data
stream and reduces the sample width to a single bit stream.
Analog Smoothing FilterThe AD28msp01’s analog smoothing filter consists of a 2nd-
order Sallen-Key continuous-time filter and a 3rd-order switched
capacitor filter. The Sallen-Key filter has a 3 dB point at
approximately 80 kHz.
The analog smoothing filter converts the 1.7280 MHz bit
stream output of the sigma-delta modulator into a low-pass
filtered, differential analog signal.
Differential Output AmplifierThe differential output amplifier produces the AD28msp01’s
analog output (VOUTP, VOUTN). It can drive loads of 2 kΩ or
greater and has a maximum differential output voltage swing of
6.312 V peak-to-peak. The output signal is dc biased to the
amplifier. Refer to “Analog Output” in the “Design Consider-
ations” section of this data sheet for more information.
The VOUTP and VOUTN outputs must be used as differential out-
puts; do not use either as a single-ended output.
SERIAL PORTThe AD28msp01 includes a full-duplex synchronous serial port
(SPORT) used to communicate with a host processor. The
SPORT is used to read and write all data and control registers
in the AD28msp01. The SPORT transfers 16-bit words, MSB
first, at a serial clock rate of 1.7280 MHz.
When the AD28msp01 exits reset, both the analog circuitry and
the digital circuitry are powered down. The serial port will not
transmit data to the host until the host sets the digital power-
down bit (PWDD) to 1 in Control Register 1. All control regis-
ters should be initialized before this bit is set.
The SPORT is configured for an externally generated receive
frame sync (SDIFS), an internally generated serial clock
(SCLK), and an internally generated transmit frame sync
(SDOFS). The host processor should be configured for an ex-
ternal serial clock and receive frame sync and an internal trans-
mit frame sync.
DSP Processor InterfaceThe AD28msp01-to-host processor interface is shown in
Figure 2.
SDO
SDOFS
SCLK
SDI
SDIFS
SERIAL DATA RECEIVE
RECEIVE FRAME SYNC
SERIAL CLOCK
FLAG
SERIAL DATA TRANSMIT
TRANSMIT FRAME SYNC
DSP PROCESSORAD28msp01Figure 2.AD28msp01-to-DSP Processor Interface
The AD28msp01’s chip select (CS) must be held high to enable
SPORT operation. CS can be used to 3-state the SPORT pins
and disable communication with the host processor.
To use the ADSP-2101 or ADSP-2111 as host DSP processor
for the AD28msp01, refer to Figure 3.
Note that the ADSP-2101’s SPORT0 communicates with the
AD28msp01’s SPORT while the ADSP-2101’s Flag Output
(FO) is used to signal the AD28msp01’s CS input. SPORT1 on
the ADSP-2101 must be configured for flags and interrupts in
this system.
Figure 3.
Figure 4 shows an ADSP-2101 assembly language program that
initializes the AD28msp01 and implements a digital loopback
AD28msp01and receive timing as well as an additional clock signal for serial
port timing.
The receive clocks are the RCONV, RBIT and RBAUD signals.
The individual clock rates are programmable and are all syn-
chronized with RCONV.
The transmit clocks are the TCONV, TBIT and TBAUD sig-
nals. The individual clock rates are programmable and are all
synchronized with TCONV.
Depending on the operating mode, the converter clocks can be
synchronized to an external clock signal (TSYNC) or can be
generated internally. The clocks can be adjusted in phase by set-
ting the appropriate phase adjust register. All the AD28msp01
Bit/Baud clocks have a 50% duty cycle except the 1600 Hz baud
rate. This baud rate has a 33%–66% duty cycle.
Resampling Interpolation FilterThe resampling interpolation filter interpolates the data from
the TCONV rate to 1.7280 MHz. The data is then resampled
(decimated) in phase with the RCONV clock. The frequency re-
sponse characteristics of the resampling interpolation filter are
identical to the frequency response characteristics of the anti-
imaging, low-pass filter/interpolation filter combination.
Figure 5 illustrates the effects of a resampling interpolation
filter.
ANALOG SIGNAL
SAMPLED AT 9600 Hz
OUTPUT OF
INTERPOLATION
FILTER
OUTPUT OF
RESAMPLING
FILTERFigure 5.Effects of Interpolation Filter
Figure 4.AD28msp01 Initialization and ADSP-2101 Loopback Routine
Serial Data OutputWhen the digital power-down bit (PWDD) of Control Register 1
is set to 1, the AD28msp01’s SPORT begins transmitting data to
the host processor. All transfers between the host processor and
the AD28msp01 consist of a serial data output frame sync
(SDOFS) followed by a 16-bit address word, then a second
frame sync followed by a 16-bit data word. Address/data word
pairs are transmitted whenever they become available. The
ADC takes precedence over the Interpolator output data. If a
new word becomes available while a serial transfer is in progress,
the current serial transfer is completed before the new word starts
transmission.
Serial Data InputThe host processor must initiate data transfers to the
AD28msp01 by asserting the serial data input frame sync
(SDIFS) high. Each of the 16-bit address word and 16-bit data
word transfers begins one serial clock cycle after SDIFS is as-
serted. The address word always precedes the data word. The
second serial data input frame sync for the data word can be as-
serted as early as the last bit of the address word is transmitted,
or any time after.
The host processor must assert SDIFS shortly after the rising
edge of SCLK and must maintain SDIFS high for one cycle be-
cause SDIFS is clocked by the SCLK falling edge. Data is then
driven from the host processor shortly after the rising edge of
the next SCLK and is clocked into the AD28msp01 on the fall-
ing edge of SCLK in that cycle. Each bit of a 16-bit address and
16-bit data word is thus clocked into the AD28msp01 on the
falling edge of SCLK (MSB first).
If SDIFS is asserted high again before the end of the present
data word transfer, it is not recognized until the falling edge of
SCLK in the last (LSB) cycle.
When the serial port receives an interpolator or DAC input
word, it writes the value to an internal register which is read by
the AD28msp01 when it is needed. This allows the host to send
data words at any time during the sample period.
NOTE:Exact SPORT timing requirements are defined in the
“Specifications” section of this data sheet.
Since the resample phase is locked to RCONV, it can be ad-
vanced or slipped by writing a signed-magnitude value to the
Receive Phase Adjust Register (Control Register 2). The phase
advance or slip is equal to the master clock period (13.824 MHz)
multiplied by the signed-magnitude 9-bit value in Control
Register 4.
The change in phase requires a maximum of two RCONV
cycles to complete. If the value written to Control Register 4 is
less than the oversampling ratio, then the change will complete
in one RCONV cycle.
Control RegistersThe AD28msp01’s six control registers configure the device for
various operating modes including filter bypass and power-
down. The AD28msp01’s host processor can read and write to
the control register through the AD28msp01’s serial port
(SPORT).
The control registers should be set up for the desired mode of
operation before bringing the AD28msp01 out of power-down
(by writing ones to the PWDA and PWDD bits in Control
Register 1).
The control registers are cleared (set to 0x0000) when the
AD28msp01 is reset.
The sampling rate should be set before writing ones to the
power-down bits. Changing the sampling rate at any other time
will force a soft reset. For more information about soft resets,
refer to the end of this section of the data sheet.
NOTE: Reserved bits should always be cleared to 0.
Control Register 0address = 0x00This register is used to:
• Enable/disable the resampling interpolation filter
• Set the external TSYNC clock rate
• Select the sampling rate
• Select the operating mode
Control Register 1address = 0x01This register is used to:
• Increase the sampling rate to 8/7 the rate selected in Control Register 0
• Power down the device
• Bypass the digital filters
AD28msp01If any low-pass filter is bypassed, the resampling interpolation filter should be disabled (in Control Register 0.)
Control Register 2 address = 0x02This register is used to:
• Select the frequency of the Receive baud clock (RBAUD)
• Select the frequency of the Receive bit clock (RBIT)
Control Register 3 address = 0x03This register is used to:
• Select the frequency of the Transmit baud clock (TBAUD)
• Select the frequency of the Transmit bit clock (TBIT)
Control Register 4address = 0x04This register is the Receive Phase Adjust Register and it is used to:
• Change the phase of the receive clocks (RBAUD, RBIT, RCONV)
Once you have written a value to the register, subsequent writes are ignored until the register is finished incrementing/decrementing
to zero.
The phase advance or slip is equal to the master clock period (13.824 MHz) multiplied by the signed-magnitude 9-bit value in
Control Register 4. The AD28msp01 decrements Control Register 4 as it adjusts the phase of RCONV. Control Register 4 will equal
zero when the phase shift is complete.
Control Register 5address = 0x05This register is the Transmit Phase Adjust Register and it is used to:
• Change the phase of the Transmit clocks (TBAUD, TBIT, TCONV)
This register must be equal to zero before its value can be
changed. Once you have written a value to the register, subse-
quent writes are ignored until the register is finished incrementing/
decrementing to zero.
The phase advance or slip is equal to the master clock period
(13.824 MHz) multiplied by the signed-magnitude 9-bit value in
Control Register 5. The AD28msp01 decrements Control Regis-
ter 5 as it adjusts the phase of TCONV. Control Register 5 will
equal zero when the phase shift is complete.
Soft ResetsCertain conditions cause the AD28msp01 to perform a soft reset;
the DSP is reset but the control register values do not change.
Table I shows when a soft reset is caused by changing the values
of certain control register bits while the device is operating.
When these bits are modified, the AD28msp01 will perform a
soft reset and start up again in the new configuration. Reserved
Table I.Soft Reset
Data RegistersThe AD28msp01 contains four data registers.
Data Register 0address = 0x06DAC Input Register (write-only): The 16-bit twos complement
values written to this register are input to the AD28msp01’s
digital-to-analog converter.
AD28msp01
Data Register 1address = 0x07Interpolation Filter Input Register (write-only): The 16-bit twos
complement values written to this register are input to the
resampling interpolation filter.
Data Register 2address = 0x08ADC Output Register (read-only): The 16-bit twos complement
values read from this register are the output of the AD28msp01’s
analog-to-digital converter.
Data Register 3address = 0x09Interpolation Filter Output Register (read-only): The 16-bit
twos complement values read from this register are the output of
the resampling interpolation filter.
Addresses 0x0A—0x1F are reserved.
Table II contains the register addresses.
Table II. Register Addresses. . . .
. . . .
Transferring Data and Control Words to the AD28msp01Data and control word transfers to the AD28msp01 can only be
initiated by the host processor. When transferring data to the
AD28msp01, the host processor specifies the destination regis-
ter by first transmitting a 16-bit address word (Figure 6) and
then transmitting the 16-bit data word. The read/write bit in the
address word must be deasserted. The serial data stream from
the host processor will consist of a sequence of alternating ad-
dress and data words. The AD28msp01 will not write the target
register until both the address word and data word are com-
pletely transferred.
14131211109876543210
READ/WRITE
ExampleTransferring the following 16-bit words to the AD28msp01 will
initialize Control Registers 0–3.
Word TransferredDescription0x0000Control Register 0 Address Word
0x0254Write this value to Control Register 0
0x0002Control Register 2 Address Word
0x0031Write this value to Control Register 2
0x0003Control Register 3 Address Word
0x0032Write this value to Control Register 3
0x0001Control Register 1 Address Word
0x0018Write this value to Control Register 1
Note that in this example the power-down bits in Control Regis-
ter 1 are released (set to 1) only after the AD28msp01 is fully
configured by writing to Control Registers 0, 2, and 3.
Transferring Data from the AD28msp01 to the HostData transfers to the host processor can only be initiated by the
AD28msp01. When transferring data the AD28msp01 first
specifies the source register by transferring a 16-bit address
word and then transfers the contents of the source register. Bits
5–14 of the address word will always be forced to zero. When
transferring data, the serial data stream from the AD28msp01
will consist of a sequence of alternating address and data words.
Transferring Control Words from the AD28msp01 to the HostAll control registers in the AD28msp01 are host-readable. To
read a control register, the host must transmit a 16-bit address
word with the Read/ Write bit set, then transmit a dummy data
word. The AD28msp01 will respond by first completing any
AD28msp01-to-Host transfer in progress. As soon as the
dummy data word is received, the device will transfer a 16-bit
word with the control register address and then transmit the
contents of the control register.
ExampleThe following data streams show how a host can read the con-
tents of an AD28msp01 control register:
HostAD28msp01
TransferTransferDescription0x8001Read Control Register 1
0x1234Dummy data word
0x AD28msp01 completes data
0x Transfer in progress
0x0001Address word
0x0023Contents of Control Register 1
Serial Port TimingAll serial transfers are synchronous. The receive data (SDI) and
receive frame sync (SDIFS) are clocked into the device on the
falling edge of SCLK. The receive frame sync (SDIFS) must be
asserted one SCLK cycle before the first data bit is transferred.
When receiving data, the AD28msp01 ignores the receive frame
sync pin until the least significant bit is being received.
When transmitting data, the AD28msp01 asserts transmit frame
sync (SDOFS) and transmit data (SDO) synchronous with the
rising edge of SCLK. Transmit frame sync is transmitted one
V.32 TSYNC ModeIn V.32 TSYNC Mode, shown in Figure 7, the AD28msp01’s
transmit circuitry is synchronized to an external TSYNC signal.
The AD28msp01 receive circuitry is sampled synchronous to
the transmit circuitry, but the data can be resampled at a differ-
ent phase by using the resampling interpolation filter.
TCONV, TBIT and TBAUD are generated internally but are
phase-locked to the external TSYNC input signal with the digi-
tal phase-locked loop. RCONV, RBIT and RBAUD are gener-
ated internally (but frequency locked to TSYNC) and can be
phase adjusted with the Receive Phase Adjust Register (Control
Register 4).
TCONV initiates a new DAC sample update, loads the ADC
register (Data Register 2), and loads the DAC register (Data
Register 0) with a new sample.
The digital resampling interpolation filter can be used for digital
resampling of the received signal. Enable this function by setting
Bit 9 in Control Register 0. The phase of the resampled signal is
adjusted with the Receive Phase Adjust Register. Samples are
loaded into the interpolator at the TCONV rate and are resampled
at the RCONV rate.
When entering V.32 TSYNC Mode, RCONV is locked to
TCONV before TCONV is locked to TSYNC. If this mode is
entered from a non-V.32 mode, the device performs a soft reset.
The time required to lock TCONV to RCONV is dependent on
the phase difference between RCONV and TCONV when en-
tering the mode.
This mode is entered by setting the Operating Mode field in
Control Register 0. The RCONV/TCONV rate can be set to
9.6 kHz, 8.0 kHz or 7.2 kHz by setting the sample rate bit field
in Control Register 0. The TBIT and TBAUD clock rates are
set by adjusting the appropriate bits in Control Register 3. The
RBIT and RBAUD clock rates are set by adjusting the appropri-
ate bits in Control Register 2. The bit rates, baud rates and
TSYNC rate can be set to any combination of clock rates listed
in the control register descriptions. The TSYNC field on Con-
trol Register 0 must be set to the frequency of the input pin.
ExampleTransferring the following word sequence to the AD28msp01
will configure the device for V.32 TSYNC Mode at the clock
rates indicated:
Word
TransferredDescription0x0000Control Register 0 address word
0x0254Enable interpolation filter, TSYNC = 7200,
sample rate = 7200, mode = V.32 TSYNC
0x0002Control Register 2 address word
0x0002RBAUD = 2400, RBIT = 7200
0x0003Control Register 3 address word
0x0023TBAUD = 1200, TBIT = 4800
0x0001Control Register 1 address word
0x0018Configure and power-up device
Figure 7.V.32 TSYNC Mode Block Diagram
AD28msp01
V.32 Internal Sync ModeIn V.32 Internal Sync Mode, shown in Figure 8, the AD28msp01’s
transmit clocks are generated internally. The receive circuitry
operates synchronous to the transmit circuitry, but the data can
be resampled at a different phase through the resampling inter-
polation filter.
TCONV, TBIT and TBAUD are generated internally and can
be phase adjusted with the Transmit Phase Adjust Register
(Control Register 5). RCONV, RBIT and RBAUD are also gen-
erated internally and can be phase adjusted with the Receive
Phase Adjust Register (Control Register 4).
TCONV initiates a new ADC sample update, loads the ADC
register (Data Register 2), and loads the DAC register (Data
Register 0) with a new sample.
The digital resampling interpolation filter can be used for digital
resampling of the received signal. Enable this function by setting
Bit 9 in Control Register 0. The phase of the resampled signal is
adjusted with the Receive Phase Adjust Register. Samples are
loaded into the interpolator at the TCONV rate and are
resampled at the RCONV rate.
When entering V.32 Internal Sync Mode, RCONV is first
locked to TCONV. RCONV is then phase adjusted whenever a
new value is written to the Receive Phase Adjust Register (Con-
trol Register 4). If this mode is entered from a non-V.32 mode,
the device performs a soft reset. The time required to lock
TCONV to RCONV is dependent on the phase difference be-
tween RCONV and TCONV when entering the mode.
This mode is entered by setting the Operating Mode field in
Control Register 0. The RCONV/TCONV rate can be set to
9.6 kHz, 8.0 kHz or 7.2 kHz by setting the sample rate bit field
in Control Register 0. The TBIT and TBAUD clock rates are
set by adjusting the appropriate bits in Control Register 3. The
RBIT and RBAUD clock rates are set by adjusting the appropri-
ate bits in Control Register 2. The bit and baud rates can be set
to any combination of clock rates listed in the control register
descriptions.
Figure 8.V.32 Internal Sync Mode Block Diagram
V.32 Loopback ModeIn V.32 Loopback Mode, shown in Figure 9, the AD28msp01’s
receive circuitry and transmit circuitry are locked together.
RCONV is generated internally and can be phase adjusted with
the Receive Phase Adjust Register (Control Register 4). RBIT,
RBAUD, TCONV, TBIT and TBAUD are all locked to
RCONV.
RCONV initiates a new DAC sample update and loads Data
Register 2 with a new sample. The RCONV rate can be set to
9.6 kHz, 8.0 kHz or 7.2 kHz by setting the sample rate bit field
in Control Register 0. The bit and baud rates can be set to
any combination of clock rates listed in the control register
descriptions.
Figure 9.Loopback Mode Block Diagram
V.32ter TSYNC ModeThis mode is identical to V.32 TSYNC Mode except all clocks
are scaled by a factor of 8/7 over the corresponding V.32
TSYNC rate. In this mode, the maximum value to which the re-
ceive and transmit phase adjust registers (Control Registers 4
and 5) may be set is +192.
Both TBIT and RBIT can be set to a 19,200 Hz rate that will
not be scaled by a factor of 8/7, by setting the appropriate fields
in Control Registers 2 and 3.
V.32ter Internal Sync ModeThis mode is identical to V.32 TSYNC Mode except all clocks
are scaled by a factor of 8/7 over the corresponding V.32
TSYNC rate. In this mode, the maximum value to which the
phase adjust registers (Control Registers 4 and 5) may be set is
+192.
Both TBIT and RBIT can be set to a 19,200 Hz rate that will
not be scaled by a factor of 8/7, by setting the appropriate fields
in Control Registers 2 and 3.
AD28msp01
Asynchronous Fallback TSYNC ModeThe Asynchronous Fallback TSYNC Mode is shown in Figure
10. TCONV, TBIT and TBAUD are generated internally but
phase locked to the external TSYNC input signal. RCONV,
RBIT and RBAUD are generated internally and can be phase
adjusted with the Receive Phase Adjust Register (Control
Register 4).
This mode is entered by setting the Operating Mode field in
Control Register 0. The RCONV/TCONV rate can be set to
9.6 kHz, 8.0 kHz or 7.2 kHz by setting the sample rate bit field
in Control Register 0. The TBIT and TBAUD clock rates are
set by adjusting the appropriate bits in Control Register 3. The
RBIT and RBAUD clock rates are set by adjusting the appropri-
ate bits in Control Register 2. The bit rates, baud rates and
TSYNC rate can be set to any combination of clock rates listed
in the control register descriptions.
Figure 10. Asynchronous Fallback TSYNC Driven Mode Block Diagram
Asynchronous Fallback ModeThe Asynchronous Fallback Mode is shown in Figure 11.
TCONV, TBIT and TBAUD are generated internally and can
be phase adjusted with the Transmit Phase Adjust Register
(Control Register 5). RCONV, RBIT and RBAUD are gener-
ated internally and can also be phase adjusted with the Receive
Phase Adjust Register (Control Register 4). The digital phase-
locked is not used in this operating mode.
This mode is entered by setting the Operating Mode field in
Control Register 0. The RCONV/TCONV rate can be set to
9.6 kHz, 8.0 kHz or 7.2 kHz by setting the sample rate bit field
in Control Register 0. The TBIT and TBAUD clock rates are
set by adjusting the appropriate bits in Control Register 3. The
RBIT and RBAUD clock rates are set by adjusting the appropri-
ate bits in Control Register 2. The bit and baud rates can be set
to any combination of clock rates listed in the control register
descriptions.
