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AD261AND-5
High Speed, Logic Isolator
REV.0
High Speed, Logic Isolator
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Isolation Test Voltage: To 3.5 kV rms
Five Isolated Logic Lines: Available in Six I/O Configurations
Logic Signal Bandwidth: 20 MHz (min)
CMV Transient Immunity: 10 kV/ms min
Waveform Edge Transmission Symmetry: 61 ns
Field and System Output Enable/Three-State Functions
Performance Rated Over –258C to +858C
UL1950, IEC950, EN60950 Certification (VDE, CE, Pending)
APPLICATIONS
PLC/DCS Analog Input and Output Cards
Communications Bus Isolation
General Data Acquisition Applications
IGBT Motor Drive Controls
High Speed Digital I/O Ports
GENERAL DESCRIPTIONThe AD261 is designed to isolate five digital control signals
to/from a microcontroller and its related field I/O components.
Six models allow all I/O combinations from five input lines to
five output lines, including combinations in between. Every
AD261 effectively replaces up to five opto-isolators.
Each line of the AD261 has a bandwidth of 20MHz (min) with
a propagation delay of only 14 ns, which allows for extremely
fast data transmission. Output waveform symmetry is maintained
to within ±1 ns of the input so the AD261 can be used to accu-
rately isolate time-based PWM signals.
All field or system output pins of the AD261 can be set to a high
resistance three-state level by use of the two enable pins. A field
output three-stated offers a convenient method of presetting
logic levels at power-up by use of pull-up/down resistors. Sys-
tem side outputs being three-stated allows for easy multiplexing
of multiple AD261s.
The isolation barrier of the AD261 B Grade is 100% tested
as high as 3.5 kV rms (system to field). The barrier design also
provides excellent common-mode transient immunity from
10 kV/μs common-mode voltage excursions of field side termi-
nals relative to the system side, with no false output triggering
on either side.
Each output is updated within nanoseconds by input logic tran-
sitions, the AD261 also has a continuous output update feature
that automatically updates each output based on the dc level of
the input. This guarantees the output is always valid 10μs after
a fault condition or after the power-up reset interval.
PRODUCT HIGHLIGHTS
Six Isolated Logic Line I/O Configurations Available: TheAD261 is available in six pin-compatible versions of I/O con-
figurations to meet a wide variety of requirements.
Wide Bandwidth with Minimal Edge Error: The AD261affords extremely fast isolation of logic signals due to its 20MHz
bandwidth and 14 ns propagation delay. It maintains a wave-
form input-to-output edge transition error of typically less thanns (total) for positive vs. negative transition.
3.5 kV rms Test Voltage Isolation Rating:The AD261
B Grade is rated to operate at 1.25 kV rms and is 100% pro-
duction tested at 3.5 kV rms, using a standard ADI test method.
High Transient Immunity:The AD261 rejects common-
mode transients slewing at up to 10 kV/μs without false trigger-
ing or damage to the device.
(Continued on page 5)
AD261–SPECIFICATIONS(Typical at TA = +258C, +5 V dcSYS, +5 V dcFLD, tRR = 50 ns max unless otherwise noted)OUTPUT CHARACTERISTICS
DYNAMIC RESPONSE
ISOLATION BARRIER RATING
POWER SUPPLY
NOTESFor best performance, bypass +5 V dc supplies to com., at or near the device (0.01 μF). +5 V dc supplies are also internally bypassed with 0.05 μF.As the supply voltage is applied to either side of the AD261, the internal circuitry will go into a power-up reset mode (all lines disabled) for about 30μs after the point
where +5 V dcSYS & FLD passes above 3.3 V.“Operating” isolation voltage is derived from the Isolation Test Voltage in accordance with such methods as found in VDE-0883 wherein a device will be “hi-pot”
tested at twice the operating voltage, plus one thousand volts. Partial discharge testing, with an acceptance threshold of 80 pC of discharge may be considered the
same as a hi-pot test (but nondestructive).Partial Discharge at 80 pC THLD.Supply Current will increase slightly, but otherwise the unit will function within specification to –40°C.
Specifications are subject to change without notice.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ABSOLUTE MAXIMUM RATINGS**Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended
periods may effect device reliability.
I/O CONFIGURATIONS AVAILABLEThe AD261 is available in several configurations. The choice of
model is determined by the desired number of input vs. output
lines. All models have identical footprints with the power and
enable pins always being in the same locations.
PIN CONFIGURATION
ENABLESYS
+5V dcSYS
5V RTNSYS
5V RTNFLD
+5V dcFLD
ENABLEFLD
ORDERING GUIDE
PIN FUNCTION DESCRIPTIONS*Function of pin determined by model. Refer to Table I.
AD261
SYSTEMFIELD
+5V dcFLD
5V RTNFLD
ENABLEFLD
5V RTNSYS
+5V dcSYS
ENABLESYS
FIELD
SYSTEM
+5V dcFLD
5V RTNFLD
ENABLEFLD
5V RTNSYS
+5V dcSYS
ENABLESYS
AD261 CONFIGURATIONS
SYSTEMFIELD
+5V dcFLD
5V RTNFLD
ENABLEFLD
5V RTNSYS
+5V dcSYS
ENABLESYS
SYSTEMFIELD
+5V dcFLD
5V RTNFLD
ENABLEFLD
5V RTNSYS
+5V dcSYS
ENABLESYS
SYSTEMFIELD
+5V dcFLD
5V RTNFLD
ENABLEFLD
5V RTNSYS
+5V dcSYS
ENABLESYS
AD261 CONFIGURATIONS(Continued from page 1)
Field and System Enable Functions:Both the isolated and
nonisolated sides of the AD261 have ENABLE pins that three-
state all outputs. Upon reenabling these pins, all outputs are
updated to reflect the current input logic level.
CE Certifiable:Simply by adding the external bypass capacitors
at the supply pins, the AD261 can attain CE certification in
most applications (to the EMC directive) and conformance to
the low voltage (safety) directive is assured by the EN60950
certification.
GENERAL ATTRIBUTESThe AD261 provides five HCMOS compatible isolated logic
lines with ≥ 10 kV/μs common-mode transient immunity.
The case design and pin arrangement provides greater than
18 mm spacing between field and system side conductors, pro-
viding CSA/IS and IEC creepage spacing consistent with 750 V
mains isolation.
The five unidirectional logic lines have six possible combina-
tions of “ins” and “outs,” or transmitter/receiver pairs; hence
there are six AD261 part configurations (see Table I).
Each 20 MHz logic line has a Schmidt trigger input and a three-
state output (on the other side of the isolation barrier) and 14 ns of
propagation delay. A single enable pin on either side of the
barrier causes all outputs on that side to go three-state and all
inputs (driven pins) to ignore their inputs and retain their last
known state.
Note: All unused logic inputs (1–5) should be tied either high or low,
but not left floating.
Edge “fidelity,” or the difference in propagation time for rising
and falling edges, is typically less than ±1 ns.
Power consumption, unlike opto-isolators, is a function of operat-
ing frequency. Each logic line barrier driver requires about 160μA
per MHz and each receiver 40 μA per MHz plus, of course, 4 mA
total idle current (each side). The supply current diminishes
slightly with increasing temperature (about –0.03%/°C).
The total capacitance spanning the isolation barrier is less thanpF.
The minimum period of a pulse that can be accurately coupled
Table I.Model Number and Pinout Function
AD261C3212–8–10/97
PRINTED IN U.S.A.
BUFFERDELAY LINEBUFFER
OUTPUT
CAPACITANCE
TOTAL DELAY = tPD 1 trr = 13ns (NO LOAD), 18ns (50pF LOAD)
tff
trr = tff = 100V x CTOTAL OUTPUT CAPACITANCE>0.5ns – NO LOAD
= 5.5ns INTO 50pF
INPUT
CAPACITANCE
EFFECTIVE
CIRCUIT
MODEL
37%
63%OUTPUT
INPUT
POSITIVE GOING
HYSTERESIS Figure 2.Typical Timing and Delay Models
22-Pin Plastic DIP
(ND-22A)
(6.35)
(1.27)
0.075 (1.91)
0.050 (1.27)0.160 (4.06)
0.140 (3.56)
0.020 3 0.010
(0.508 3 0.254)
16 PLACES
(2.54)
MAX
(11.18)
MAX
(8.89)
OUTLINE DIMENSIONSDimensions shown in inches and (mm).
Logic information is sent across the barrier as “set-hi/set-lo”
data that is derived from logic level transitions of the input. At
power-up or after a fault condition, an output might not repre-
sent the state of the respective channel input to the isolator. An
internal circuit operates in the background which interrogates
all inputs about every 5μs and in the absence of logic transi-
tions, sends appropriate “set-hi” or “set-lo” data across the
barrier.
Recovery time from a fault condition or at power-up is thus
between 5 μs and 10 μs.
DRIVER
DATA
RECEIVER
OUTPUT
BUFFER
GATED
TRANSPARENT
LATCH
SCHMITT
TRIGGER
BUFFER
CONTINUOUS
UPDATE CIRCUIT
3.5kV
ISOLATION
BARRIER
DATA IN
ENABLEENABLE
OUTFigure 1.Simplified Block Diagram
