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AD1991ASV
Class D/1-Bit Audio Power Amplifier Output Stage
REV.0
Class D/1-Bit Audio Power Output Stage
FUNCTIONAL BLOCK DIAGRAMS
2-Channel Mode
4-Channel Mode
FEATURES
Class D/1-Bit Audio Power Output Stage
5 V Analog and Digital Supply Voltages
Power Stage Power Supply 8 V to 20 V
Output Power @ 0.1% THD + N
Stereo Mode
2 � 20 W @ 4 � @ 14.4 V
2 � 20 W @ 8 � @ 20 V
Mono Mode
1 � 40 W @ 4 � @ 20 V
RON <320 m� (per Transistor)
Efficiency >85% @ Full Power/8 �
Clickless Mute Function
Turn-On and Turn-Off Pop Suppression
Short-Circuit Protection
Overtemperature Protection
Data Loss Protection
2-Channel BTL Outputs or
4-Channel Single-Ended Outputs
52-Lead Exposed Pad TQFP Package
Low Cost DMOS Process
APPLICATIONS
PC Audio Systems
Minicomponents
Automotive Amplifiers
Home Theater Systems
Televisions
GENERAL DESCRIPTIONThe AD1991 is a 2-channel BTL or 4-channel single-ended
class D audio power output stage. The part is configured during
reset to be in either 2-channel mode or 4-channel mode.
To protect the IC as well as the connected speakers, the AD1991
provides turn-on and turn-off pop suppression, short-circuit
protection, and overtemperature shutdown. To control the IC,
a power-down/reset input and a mute pin are available.
The output stage can be operated over a power supply range
from 8 V to 20 V.
In 2-channel mode, Transistors A1, B2, C1, and D2 are turned
on by a Logic 1 on inputs INA and INC, and Transistors A2,
B1, C2, and D1 are turned on by a Logic 0 on inputs INA and
INC. In 4-channel mode, Transistors A1, B1, C1, and D1 are
turned on by a Logic 1 on the four inputs, and Transistors A2,
B2, C2, and D2 are turned on by a Logic 0 on the four inputs
(see the Functional Block Diagrams).
AD1991–SPECIFICATIONS1NOTESPerformance of both channels is identical.Measurement requires PWM modulator.
Specifications subject to change without notice.
DIGITAL TIMING CHARACTERISTICSSpecifications subject to change without notice.
(Guaranteed over –40�C to +85�C, AVDD = DVDD = 5 V � 10%, PVDDX = 20 V � 10%,
Edge Speed = Slowest, Nonoverlap Time = Shortest.)
(AVDD = 5 V, DVDD = 5 V, PVDDX = 20 V, Ambient Temperature = 25�C,
Load Impedance = 8 �, unless otherwise noted.)
AD1991Figure 1.Output Timing
Figure 2.RESET and Mode Timing
Figure 3.MUTE Timing
AD1991
ABSOLUTE MAXIMUM RATINGS1(TA = 25°C, unless otherwise noted.)
AVDD, DVDD to AGND, DGND . . . . . . . . . .–0.3 V to +6.5 V
PVDDX to PGNDx2 . . . . . . . . . . . . . . . . . . .–0.3 V to +30.0 V
AGND to DGND to PGNDx . . . . . . . . . . . .–0.3 V to +0.3 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +0.5 V
Operating Temperature Range (Ambient)
Industrial . . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . .150°C
θJC Thermal Resistance3 . . . . . . . . . . . . . . . . . . . . . . .1°C/W
Lead Temperature
Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .260°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . .215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .220°C
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD1991 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2Including any induced voltage due to inductive load.
3With respect to the temperature of the exposed pad.
ORDERING GUIDE
PIN CONFIGURATION
PGND1
PGND1
OUTA
PGND1
PGND1
PGND1
PGND2
PGND2
PGND2
PGND2
OUTA
OUTA
OUTB
OUTB
OUTB
PVDD1
PVDD1
PVDD1
OUTC
OUTC
OUTC
OUTD
OUTD
OUTD
PVDD2
PVDD2
PVDD2
PGND1PGND1AGNDAGNDAGNDAGNDPGND2PGND2PGND2MODE1MODE0AV
DGND
ERR3ERR2ERR1ERR0
INAINB
MUTE
RST
/PDN
CLK
INDINC
PIN FUNCTION DESCRIPTIONS8, 9, 10
11, 12, 13
27, 28, 29
30, 31, 32
33, 34, 35
36, 37, 38
39, 40, 41, 42
43, 45, 48, 49
AD1991
FUNCTIONAL DESCRIPTION
Device ArchitectureThe AD1991 is an 8-transistor, audio, power output stage. The
AD1991 is arranged internally as four transistor pairs that can
be used as two H-bridge outputs (2-channel mode) or as four
single-ended outputs (4-channel mode), using either two or four
TTL compatible inputs to control the transistors. A dead time
is automatically provided between the switching of the high-
side transistor and low-side transistor when the control inputs
change level, to ensure that both the high-side transistor and
low-side transistor are never on at the same time.
Clock Source and Channel Mode SelectionWhen the AD1991 is brought out of reset, the logic levels on
MODE0 and MODE1 are latched internally. MODE0 determines
the internal state machine clock source. MODE1 determines the
channel mode and the function of ERR0 (see Tables I and II.)
When the internal clock is used, the CLK pin should not be
connected.
Table I.Clock Source Selection
Table II.Channel Mode Selection
2-Channel ModeTwo loads are connected differentially—across OUTA and OUTB
and across OUTC and OUTD. Inputs INB and IND are unused
and should be tied to an appropriate dc voltage (see the Edge
Speed and Nonoverlap Settings section). In this mode, ERR0 is
an error output used to indicate data loss, which occurs when
there are no transitions on INA or INC for more than 50ms.
This signal condition is hazardous in 2-channel mode because it
can cause a potentially large and harmful dc voltage across the
differential loads. Table III shows the input/output relationship.
Table III.Input/Output Relationship in 2-Channel Mode
4-Channel ModeThe 4-channel mode has two types of configuration: audio and
power supply. Neither of these configurations require data loss
detection. In the audio configuration, each single-ended load is
connected to the output through a blocking capacitor, which
prevents dc from reaching the load, thereby negating the need
for data loss detection. While in the power supply configuration,
it is desired to maintain a dc voltage on the load, also negating
the need for data loss detection. When used in the power supply
configuration, the four low-side transistors can also be disabled
and left permanently open if desired. This allows the loads to be
driven by switching only the high-side transistor on and off.
ERR0 is an input in 4-channel mode and is used to select
whether the four low-side transistors are enabled or disabled,
with 0 selecting disabled and 1 selecting enabled. TableIV
summarizes the function of ERR0 in this mode. TableV shows
the input/output relationship.
Table IV.ERR0 Function in 4-Channel Mode
Table V.Input/Output Relationship in 4-Channel Mode
1-Channel ModeOne load is connected differentially—across OUTA and OUTC,
and OUTB and OUTD. This mono operation is established
by configuring the part for 2-channel mode and externally
connecting INA to INC, OUTA to OUTC, and OUTB to
OUTD (see Figure4).
Thermal ProtectionThe AD1991 features thermal protection. When the die tempera-
ture exceeds approximately 135°C, the thermal warning error
output (ERR2) is asserted. If the die temperature exceeds
approximately 150°C, the thermal shutdown error output (ERR3)
is asserted. If this occurs, the part shuts down to prevent damage
to the part. When the die temperature drops below approximately
120°C, both error outputs de-assert and the part returns to nor-
mal operation.
Overcurrent ProtectionThe AD1991 features overcurrent or short-circuit protection. If
the current through any power transistors exceeds 5A, the part
is muted and the overcurrent error output (ERR1) is asserted.
This is a latched error and does not clear automatically. To clear
the error condition and restore normal operation, the part must
be reset or MUTE must be asserted and de-asserted.
