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AD1985JST-AD1985JST-REEL
AC ?7 SoundMAX Codec
AC ’97 SoundMAX® CodecRev. A
AC ’97 2.3 COMPLIANT FEATURES
6 DAC channels for 5.1 surround
Greater than 90 dB dynamic range
20-bit resolution on all DACs
S/PDIF Output
Integrated stereo headphone amplifiers
Variable rate audio
Double rate audio (fS = 96 kHz)
Line-level mono phone input
High quality CD mixer input
Selectable MIC input with preamp
AUX and line in stereo inputs
External amplifier power down (EAPD)
Power management modes
Jack sensing and peripheral enumeration/identification
48-lead LQFP package
ENHANCED FEATURES
Integrated parametric equalizer (EQ)
Stereo microphone with preamplifiers
Integrated PLL for system clocking
Variable sample rate 7 kHz to 96 kHz
7 kHz to 48 kHz in 1 Hz increments
96 kHz for double rate audio
Advanced jack sense with auto topology switching
Software enabled VREFOUT for microphones and external
power amp
Software enabled outputs for jack sharing
Auto down-mix and channel spreading
Microphone to mono output
Stereo microphone analog passthrough to outputs
Built-in stereo microphone and Center/LFE pin sharing
Selectable Center/LFE tip/ring swapping to support various
speaker products
FUNCTIONAL BLOCK DIAGRAM
ID0
ID1
RESET
SYNC
BITCLK
SDATA_OUT
SDATA_IN
JS0JS1JS2JS3EAPD
MIC1
MIC2
PHONE_IN
CD_L
CD_GND
CD_R
AUX_L
AUX_R
LINE_IN_L
LINE_IN_RLFE_OUTCENTER_OUTLINE_OUT_LMONO_OUTLINE_OUT_RSURR_OUT_L/HP_OUT_LSURR_OUT_R/HP_OUT_R
VREF
VREFOUT
XTL_OUTXTL_INSPDIF_OUT03610-A
Figure 1.
TABLE OF CONTENTS Detailed Functional Block Diagram..............................................3
Specifications.....................................................................................4
Analog Input.................................................................................4
Master Volume..............................................................................4
Programmable Gain Amplifier—ADC......................................4
Analog Mixer—Input Gain/Amplifiers/Attenuators...............5
Digital Decimation and Interpolation Filters...........................5
Analog-to-Digital Converters.....................................................5
Digital-to-Analog Converters.....................................................5
Analog Output..............................................................................6
Static Digital Specifications.........................................................6
Power Supply.................................................................................6
Power-Down States......................................................................7
Clock Specifications.....................................................................7
Timing Parameters.......................................................................8
Absolute Maximum Ratings..........................................................10
Environmental Conditions........................................................10
ESD Caution................................................................................10
Pin Configuration and Functional Descriptions........................11
Pin Descriptions.........................................................................11
Indexed Control Registers.........................................................13
Outline Dimensions.......................................................................47
Ordering Guide...........................................................................47
REVISION HISTORY
3/04—Data Sheet changed from Rev. 0 to Rev. A Updated Format.................................................................Universal
Changes to Figure 1.........................................................................1
Changes to Figure 2.........................................................................3
Changes to Table 4...........................................................................4
Changes to Tables 5, 7, and 8..........................................................5
Changes to Table 12........................................................................7
Changes to Pin Configuration.....................................................11
Changes to Circuit Layout Note..................................................11
Changes to Indexed Control Registers.......................................13
Changes to Master Volume Register (Index 0x02)....................15
Changes to Headphone Volume Register (Index 0x04)...........16
Changes to Mono Volume Register (Index 0x06).....................17
Changes to PC Beep Register (Index 0x0A)..............................18
Changes to Microphone Volume Register (Index 0x0E)..........19
Changes to AUX In Volume Register (Index 0x16)..................21
Changes to Record Select Control Register (Index 0x1A).......22
Changes to Record Gain Register (Index 0x1C).......................23
Changes to Extended Audio ID Register (Index 0x28)............27
Changes to Center/LFE Volume Control
Register (Index 0x36)....................................................................30
Changes to Surround Volume Control Register
(Index 0x38)...................................................................................31
Changes to Jack Sense/Audio Interrupt/Status Register
(Index 0x72)...................................................................................36
Changes to Miscellaneous Control Bits (Index 0x76)..............39
Changes to Advanced Jack Sense Register (Index 0x78)..........41
Updated Outline Dimensions......................................................47
Updated Ordering Guide..............................................................47
3/03—Revision 0: Initial Version DETAILED FUNCTIONAL BLOCK DIAGRAM
ID0ID1R
ESET
SYN
BITCLK
ATA_
JS0
JS2
JS3
LINE
LINE
LFE_OUT
NTE
LINE
MONO_
LINE
URR_
URR_03610-A
OMS:
0x74 D9
DEF=0(MIC_1/2)
00= +2.25V01= HIGH Z10= +3.7V
MONO_OUT:0dB to -46.5dBDEF=0x8000 0dB/MUTED
LINE_OUT:0dB to -46.5dBDEF=0x8000 0dB/MUTED
LINE_OUT:0dB to -46.5dBDEF=0x8000 0dB/MUTED
AC97 MODE:
ADI MODE:0dB to -46.5dBDEF 0x8000 0dB/MUTED
AC97 MODE:
ADI MODE:0dB to -46.5dBDEF 0x8000 0dB/MUTED
OMS: 0x74 D9
DEF=0(MIC_1/2)
CLDIS:DEF=0(enabled)
2CMIC: 0x76 D7
DEF=0 (MS Sel)
MS: 0x20 D8
Note:
VREFOUT: 0x76 D3-D2
DEF=00 (+2.25V)
Figure 2. Detailed Functional Block Diagram
SPECIFICATIONS
Table 1. Test Conditions, Unless Otherwise Noted
ANALOG INPUT
Table 2. INPUT VOLTAGE
LINE_IN, CD, AUX, PHONE_IN 1 2.83
MIC_IN with +30 dB Preamp 0.032 0.089
MIC_IN with +20 dB Preamp 0.1 0.283
MIC_IN with +10 dB Preamp 0.316 0.894
MIC_IN with 0 dB Preamp 1 2.83
Input Impedance1 20
MASTER VOLUME
Table 3.
PROGRAMMABLE GAIN AMPLIFIER—ADC
Table 4.
ANALOG MIXER—INPUT GAIN/AMPLIFIERS/ATTENUATORS
Table 5.
DIGITAL DECIMATION AND INTERPOLATION FILTERS1
Table 6.
ANALOG-TO-DIGITAL CONVERTERS
Table 7.
DIGITAL-TO-ANALOG CONVERTERS
Table 8. ANALOG OUTPUT
Table 9. Note that setting VREFOUT to 0 V reduces crosstalk when Center/LFE is sharing the MIC jack. The Center/LFE crosstalk should be better than −60 dB at 100 Hz when sharing
with a stereo microphone application circuit.
STATIC DIGITAL SPECIFICATIONS
Table 10.
POWER SUPPLY
Table 11. 1 Guaranteed, not tested.
POWER-DOWN STATES1
Table 12.
CLOCK SPECIFICATIONS
Table 13. 1 Currents measured with VREFOUT unloaded. PR bits are controlled in Registers 0x2A and 0x26.
TIMING PARAMETERS Guaranteed over operating temperature range.
Table 14. Guaranteed, not tested.
2 Output jitter directly dependent on crystal input jitter; maximum specified for noncrystal operation.
RESET
BIT_CLK
SDATA_IN
tRST_LOW
tTRI2ACTV
tTRI2ACTV Figure 3. Cold Reset Timing (Codec is Supplying the Bit_CLK Signal)
SYNC
BIT_CLK
03610-0-004 Figure 4. Warm Reset Timing
BIT_CLK
SYNC
tCLK_LOW
tCLK_HIGH
tCLK_PERIOD
tSYNC_LOW
tSYNC_PERIOD Figure 5. Clock Timing
BIT_CLK
SYNC
SDATA_IN
SDATA_OUT
tRISECLKtFALLCLK
tRISESYNCtFALLSYNC
tRISEDINtFALLDIN
tRISEDOUTtFALLDOUT
03610-0-006 Figure 6. Signal Rise and Fall Times
BIT_CLK
SYNC
SDATA_IN
BIT_CLK NOT TO SCALE
03610-0-007 Figure 7. AC Link Low Power Mode Timing
BIT_CLK
SDATA_OUT
SDATA_IN
SYNC
03610-0-008 Figure 8. AC Link Low Power Mode Timing
RESET
SDATA_OUT
EAPD, SPDIF_OUT
AND DIGITAL I/O
03610-0-009 ABSOLUTE MAXIMUM RATINGS
Table 15. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating TCASE = Case Temperature in °C
PD = Power Dissipation in W
θJA = Thermal Resistance (Junction to Ambient)
θJC = Thermal Resistance (Junction to Case)
Table 16. Thermal Resistance All measurements per EIA/JESD51 with 2S2P test board per EIA/JESD51-7.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SPD
ID1ID0AV
SS3
DD3S
URR/HP
UT_
SS2
URR/HP
UT_
DD2
NC = NO CONNECT
E_IN
AUX
AUX
JS1JS0
CD_
CD_
ND_
CD_
LINE
IN_
LINE
IN_
DVDD1
XTL_IN
XTL_OUT
DVSS1
SDATA_OUT
BIT_CLK
DVSS2
SDATA_IN
DVDD2
SYNC
RESET
JS3
LINE_OUT_R (FRONT)/SURR_R
LINE_OUT_L (FRONT)/SURR_L
AVDD4
JS2
LFE_OUT
CENTER_OUT
AFILT2
AFILT1
VREFOUT
VREF
AVSS1
AVDD103610-A
Figure 10. 48-Lead LQFP Pin Configuration
Circuit Layout Note: In normal operation, Surround and Line Out are swapped to provide headphone drive on line outputs. Therefore, Pins 35 and 36 become the surround L/R outputs and Pins 39 and 41 become the Line Out (Front) L/R outputs with headphone drive. See Bits LOSEL and HPSEL in Register 0x76 for details.
PIN FUNCTION DESCRIPTIONS
Table 17. Digital I/O
Table 18. Chip Selects/Clock Strapping
Mnemonic Pin No.
Table 19. Jack Sense/EAPD
Table 20. Analog I/O
Table 21. Filter/Reference
Table 22. Power and Ground Signals
Table 23. No Connects INDEXED CONTROL REGISTERS NOTES
Odd register addresses are aliased to the next lower even address.
Registers not shown and bits containing an X are assumed to be reserved.
Reserved registers should not be written. Zeros should be written to reserved bits.
1 For AC ‘97 compatibility, these RM bits must be enabled before they can have any effect. X
Reset (Index 0x00) Note: Writing any value to this register performs a register reset, which causes all registers (except Register 0x74) to revert to their default values. Register 0x74 will only
reset Bits CSWP (D3), LBKS[1:0] (D[6:5]), and OMS (D9). The REGM and serial configuration bits are reset only by an external hardware reset.
Reading this register returns the ID code of the part and a code for the type of 3D stereo enhancement.
ID[9:0] Identify Capability: The ID decodes the capabilities of AD1985 based on the following: SE[4:0] Stereo Enhancement. The AD1985 does not provide hardware 3D stereo enhancement (all bits are 0).
Master Volume Register (Index 0x02) For AC ’97 compatibility, Bit D7 (MMRM) is available only by setting the MSPLT bit in Register 0x76. The MSPLT bit enables separate mute bits for the left and right
channels.
This register controls the LINE_OUT volume and mute bits.
Each volume subregister contains five bits, generating 32
volume levels with increments of 1.5 dB each.
AC ’97 defines the 6-bit volume registers, therefore, to maintain
compatibility whenever the D5 or D13 bit is set to 1, its
respective lower five volume bits are automatically set to 1 by
the codec logic. On readback, all lower five bits will read 1s
whenever these bits are set to 1.
Note that depending on the state of the AC97NC bit in Register
0x76, this register has the following additional functionality:
• For AC97NC = 0, the register controls the LINE_OUT output
attenuators only.
• For AC97NC = 1, the register controls the LINE_OUT, center,
and LFE output attenuators.
RMV[4:0] Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from
0 dB to a maximum attenuation of 46.5 dB.
MMRM Right Channel Mute. Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel
separately from the MM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1.
Volume Settings for Master and Headphone Note: x in the above table is a wild card, meaning the value has no effect.
For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If
MSPLT is not set, Bit D7 has no effect.
Headphone Volume Register (Index 0x04) For AC ’97 compatibility, Bit D7 (HPRM) is available only by setting the MSPLT bit in Register 0x76. The MSPLT bit enables separate mute bits for the left and right
channels.
This register controls the headphone volume for both stereo
channels and mute bits. Each volume subregister contains five
bits, generating 32 volume levels with increments of 1.5 dB each.
AC ’97 defines the 6-bit volume registers, therefore, to maintain
compatibility whenever the D5 or D13 bit is set to 1, its
respective lower five volume bits are automatically set to 1 by
the codec logic. On readback, all lower five bits will read 1s
whenever these bits are set to 1 (see the Volume Settings for
Master and Headphone table on the previous page).
Note that depending on the state of the AC97NC bit in Register
0x76, this register has the following additional functionality:
• For AC97NC = 0, the register has no control over the
SURR_OUT/HP_OUT outputs (see Register 0x38).
• For AC97NC = 1, the register controls the
SURR_OUT/HP_OUT output attenuators.
Mono Volume Register (Index 0x06) This register controls the mono output volume and mute bit.
The volume register contains five bits, generating 32 volume
levels with increments of 1.5 dB each.
AC ’97 defines the 6-bit volume registers, therefore, to maintain
compatibility whenever the D5 bit is set to 1, its respective lower
five volume bits are automatically set to 1 by the codec logic. On
readback, all lower five bits will read 1s whenever this bit is set
to 1.
Volume Settings for Mono Note that the x in the above table is a wild card, meaning the value has no effect.
PC Beep Register (Index 0x0A) This register controls the level and frequency for the digital PC beep generated by the codec. Please note that PC Beep should be muted
when not in use.
PCBV[3:0] Controls the volume of the generated signal. Each step corresponds to approximately 3 dB of attenuation. The
MSB of the register is the mute bit. When this bit is set to 1, the level for the signal is set at –∞ dB.
The register default value is 0x8000, which corresponds to 0 dB attenuation with mute on.
Phone_In Volume Register (Index 0x0C)
Volume Settings for Phone and MIC Note that the x in the above table is a wild card, meaning the value has no effect.
Microphone Volume Register (Index 0x0E) This register controls the volume, gain boost, and mute for the gain/attenuators on both the MIC1 and MIC2 paths to the mixer. There is
no separate control for left and right on this path. The signal paths must be identical, hence the single control for both.
Line In Volume (Index 0x10) 1 For AC ’97 compatibility, Bit D7 (LVRM) is available only by setting the MSPLT bit in Register 0x76. The MSPLT bit enables separate mute bits for the left and right
channels.
Volume Settings for Line In, CD Volume, AUX, and PCM Out For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels. If
MSPLT is not set, RM bit has no effect.
Note that the x in the above table is a wild card, meaning the value has no effect.
CD Volume Register (Index 0x12) 1 For AC97 compatibility, Bit D7 (CDRM) is available only by setting the MSPLT bit in Register 0x76. The MSPLT bit enables separate mute bits for the left and right
channels. See the Volume Settings for Line In, CD Volume, AUX, and PCM Out table.
AUX In Volume Register (Index 0x16) For AC ’97 compatibility, Bit D7 (AVRM) is available only by setting the MSPLT bit in Register 0x76. The MSPLT bit enables separate mute bits for the left and right
channels. See the Volume Settings for Line In, CD Volume, AUX, and PCM Out table.
RAV[4:0] Right AUX Volume. Allows setting the AUX right channel gain/attenuator to one of 32 levels. The LSB represents 1.5
dB, and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
PCM Out Volume (Index 0x18) 1 For AC ’97 compatibility, Bit D7 (OMRM) is available only by setting the MSPLT bit in Register 0x76. The MSPLT bit enables separate mute bits for the left and right
channels. See the Volume Settings for Line In, CD Volume, AUX, and PCM Out table.
Note that depending on the state of the AC97NC bit in Register 0x76, this register has the following additional functionality: For AC97NC = 0, the register also controls the surround, center, and LFE DAC gain/attenuators. For AC97NC = 1, the register controls the PCM out volume only.
Record Select Control Register (Index 0x1A) This register is used to select the record source, independently for the right and left channels.
For single MIC recording, see the MS bit (Register 0x20) for MIC1 and MIC2 input selection.
For dual MIC recording, see the 2CMIC bit (Register 0x76) to enable simultaneous recording into L/R channels.
For output line sharing for the microphones, see the OMS bit (Register 0x74) to swap between the MIC1/MIC2 and C/LFE pins.
The default value is 0x0000, which corresponds to the MIC input for both channels.
Record Gain Register (Index 0x1C) For AC ’97 compatibility, Bit D7 (IMRM) is available only by setting the MSPLT bit in Register 0x76. The MSPLT bit enables separate mute bits for the left and right
channels.
General Purpose Register (Index 0x20)
