AD1981B Fast Delivery |IC PHOENIX CO.,LIMITED

AD1981B ,AD1981B AC'97 SoundMAX?CodecSPECIFICATIONSDAC Test ConditionsSTANDARD TEST CONDITIONS, UNLESSCalibratedOTHERWISE NOTED–3 dB Att ..
AD1981BBSTZ , AC 97 SoundMAX Codec
AD1981BJST ,AC ?7 SoundMAX CodecFEATURES Power Management SupportS/PDIF Output, 20 Bits Data Format, Supporting 48-Lead LQFP Packag ..
AD1981BJST ,AC ?7 SoundMAX CodecSPECIFICATIONSDAC Test ConditionsSTANDARD TEST CONDITIONS, UNLESSCalibratedOTHERWISE NOTED–3 dB Att ..
AD1981BJST ,AC ?7 SoundMAX CodecFEATURESIntegrated Stereo Headphone AmplifierStereo MIC Preamps SupportVariable Sample Rate AudioBu ..
AD1981B-JST ,AC ?7 SoundMAX CodecFEATURES Mono Output for Speakerphone or Internal SpeakerAC ’97 2.3 COMPATIBLE
AD8392AAREZ-RL , Low Power, High Output Current, Quad Op Amp, Dual-Channel ADSL/ADSL2 Line Driver
AD8392AAREZ-RL , Low Power, High Output Current, Quad Op Amp, Dual-Channel ADSL/ADSL2 Line Driver
AD8392ARE ,Low Power, High Output Current, Dual Channel ADSL/ADSL2+ Line DriverSPECIFICATIONS VS = ±12 V or +24 V, RL = 100 Ω, G = +5, PD = (0, 0), T = 25°C, unless otherwise not ..
AD8392ARE ,Low Power, High Output Current, Dual Channel ADSL/ADSL2+ Line DriverGENERAL DESCRIPTION The AD8392 is comprised of four high output current, low power consumption, op ..
AD8392ARE ,Low Power, High Output Current, Dual Channel ADSL/ADSL2+ Line Driverapplications. The AD8392 is available in two thermally enhanced packages, a 28-lead TSSOP EP (AD839 ..
AD8392ARE-REEL7 ,Low Power, High Output Current, Dual Channel ADSL/ADSL2+ Line Driverapplications (20.4 dBm line NC 8 21 V 3, 4CCpower, 5.5 CF) V 39 20 V 4OUT OUTThree active power mod ..

AD1981B
AD1981B AC'97 SoundMAX?Codec
REV.A
AC ’97 SoundMAXCodec
FUNCTIONAL BLOCK DIAGRAM
FEATURES
AC ’97 2.3 COMPATIBLE FEATURES
S/PDIF Output, 20 Bits Data Format, Supporting
48 kHz and 44.1 kHz Sample Rates
Integrated Stereo Headphone Amplifier
Variable Sample Rate Audio
External Audio Power-Down Control
Greater than 90 dB Dynamic Range
Stereo Full-Duplex Codec
20-Bit PCM DAC
3 Analog Line-Level Stereo Inputs for
Line-In, AUX, and CD
Mono Line-Level Phone Input
Dual MIC Input with Built-In Programmable Preamp
High Quality CD Input with Ground Sense
Mono Output for Speakerphone or Internal Speaker Power
Management Support
48-Lead LQFP Package
ENHANCED FEATURES
Stereo MIC Preamps Support
Built-In Digital Equalizer Function for Optimized Speaker
Sound
Full-Duplex Variable Sample Rates from 7040 Hz to 48 kHz
with 1 Hz Resolution
Jack Sense Pins Provide Automatic Output Switching
Software Programmed VREFOUT Output for Biasing
Microphone and External Power Amp
Split Power Supplies: 3.3 V Digital and 5 V Analog
Multiple Codec Configuration Options
MIC1
MIC2
PHONE_IN
CD_L
CD_GND
CD_R
AUX_L
AUX_R
LINE_IN_L
MONO_OUT
HP_OUT_LLINE_OUT_LLINE_OUT_R
HP_OUT_R
VREF
VREFOUT
LINE_IN_R
XTL_OUTXTL_INSPDIF
ID0
ID1
RESET
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
JS0JS1EAPD
AD1981B
STANDARD TEST CONDITIONS, UNLESS
OTHERWISE NOTED
Temperature25°C
Digital Supply (VDD)3.3 V
Analog Supply (VCC)5.0 V
Sample Rate (FS)48 kHz
Input Signal1008 Hz
Analog Output Pass Band20 Hz to 20 kHz
DAC Test Conditions
Calibrated
–3 dB Attenuation Relative to Full Scale
0 dB Input
10 kΩ Output Load (LINE_OUT)
32 Ω Output Load (HP_OUT)
ADC Test Conditions
Calibrated
0 dB Gain
Input –3.0 dB Relative to Full Scale
PROGRAMMABLE GAIN AMPLIFIER—ADC
ANALOG MIXER—INPUT GAIN/AMPLIFIERS/ATTENUATORS
DIGITAL DECIMATION AND INTERPOLATION FILTERS
–SPECIFICATIONS
AD1981B
ANALOG OUTPUT
AD1981B
*Values presented with VREFOUT not loaded.
Specifications subject to change without notice.
NOTESGuaranteed but not tested.Measurements reflect main ADC.
Specifications subject to change without notice.
TIMING PARAMETERS(Guaranteed over Operating Temperature Range)
AD1981B
Figure 1.Cold Reset Timing (Codec is Supplying the Bit_CLK Signal)
Figure 2.Warm Reset Timing
Figure 3.Clock Timing
Figure 4.Signal Rise and Fall Times
AD1981B
Figure 5.AC-Link Low Power Mode Timing
Figure 6.AC-Link Low Power Mode Timing, SYNC and BIT_CLK Chopped
Figure 7.ATE Test Mode
PIN CONFIGURATION
48-Lead LQFP
DVDD1
XTL_IN
XTL_OUT
DVSS1
SDATA_OUT
BIT_CLK
DVSS2
SDATA_IN
DVDD2
SYNC
RESET
LINE_OUT_R
LINE_OUT_L
AVDD4
AVSS4
AFILT4
AFILT3
AFILT2
AFILT1
VREFOUT
VREF
AVSS1
AVDD1
PHONE_IN
AUX_L
AUX_R
JS1JS0
CD_L
CD_GND_REF
CD_R
MIC1MIC2
LINE_IN_LLINE_IN_R
SPDIFEAPDID1ID0AVHP_OUT_RAV
HP_OUT_LAV
MONO_OUT
NC = NO CONNECT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
ORDERING GUIDE
*ST = Low Profile Quad Flatpack
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
Power Supplies
Digital (DVDD) . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +3.6 V
Analog (AVDD) . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6.0 V
Input Current (Except Supply Pins) . . . . . . . . . . . . . .±10 mA
Signals Pins
Digital Input Voltage . . . . . . . . . . . . .–0.3 V to DVDD + 0.3 V
Analog Input Voltage . . . . . . . . . . . .–0.3 V to AVDD + 0.3 V
Ambient Temperature Range (Operating) . . . . . . .0°C to 70°C
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ENVIRONMENTAL CONDITIONS*
Ambient Temperature Rating (TQFP Package)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
�JA Thermal Resistance (Junction-to-Ambient)
�JC Thermal Resistance (Junction-to-Case)
*All measurements per EIA-JESD51 with 2S2P test board per
EIA-JESD51-7
AD1981B
PIN FUNCTION DESCRIPTIONS
Indexed Control Registers
NOTES
All registers not shown. Bits containing an X are assumed to be reserved.
Odd register addresses are aliased to the next lower even address.
Reserved registers should not be written.
Zeros should be written to reserved bits.
*For AC ’97 compatibility, Bit D7 (RM) is only available by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, RM bit has no effect.
AD1981B
Reset Register (Index 00h)
NOTES
X in the above table is a wild card and has no effect on the value.
Writing any value to this register performs a register reset that causes all registers to revert to their default values (except 74h, which forces the serial configuration).
Reading this register returns the ID code of the part and a code for the type of 3D stereo enhancement.
ID[9:0] Identify Capability. The ID decodes the capabilities of AD1981B based on the following:
SE[4:0] Stereo Enhancement. The AD1981B does not provide hardware 3D stereo enhancement (all bits are zeros).
Master Volume Register (Index 02h)For AC ‘97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved.
Refer to Table I for examples. This register controls the Line_Out volume controls for both stereo channels and the mute bit. Each
volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume
registers, to maintain compatibility whenever the D5 or D13 bits are set to “1,” their respective lower five volume bits are automati-
cally set to “1” by the codec logic. On readback, all lower five bits will read “1s” whenever these bits are set to “1.”
Headphones Volume Register (Index 04h)
*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved.
Refer to Table I for examples. This register controls the headphone volume controls for both stereo channels and mute bit. Each
volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume
registers, to maintain compatibility, whenever the D5 or D13 bits are set to “1,” their respective lower five volume bits are automati-
cally set to “1” by the codec logic. On readback, all lower five bits will read “1s” whenever these bits are set to “1.”
Table I.Volume Settings for Master and Headphone
Reg. 76h
*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, RM bit has no effect.
X in the above table is a wild card and has no effect on the value.
AD1981B
Mono Volume Register (Index 06h)
All registers not shown and bits containing an X are assumed to be reserved.
Refer to Table II for examples. This register controls the mono output volume and mute bit. The volume register contains five bits,
generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume registers, to maintain compatibility,
whenever the D5 bit is set to “1,” their respective lower five volume bits are automatically set to “1” by the codec logic. On
readback, all lower five bits will read “1s” whenever this bit is set to “1.”
Table II.Volume Settings for Mono
x in the above table is a wild card and has no effect on the value.
All registers not shown and bits containing an X are assumed to be reserved. Refer to Table III for examples.
Phone Volume Register (Index 0Ch)
All registers not shown and bits containing an X are assumed to be reserved. Refer to Table III for examples.
MIC Volume Register (Index 0Eh)
All registers not shown and bits containing an X are assumed to be reserved. Refer to Table III for examples.
Table III.Volume Settings for Phone and MIC
x in the above table is a wild card, and has no effect on the value.
Line-In Volume Register (Index 10h)
*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, the RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.
CD Volume Register (Index 12h)
*For AC ’97 compatibility, Bit D7 (RM) is only available by setting the MSPLT bit, Register 76h. The MSPLT Bit enables separate mute bits for the left and right
channels. If MSPLT is not set, the RM Bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.
AD1981B
AUX Volume Register (Index 16h)
*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.
PCM-Out Volume Register (Index 18h)
*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.

Partno	Mfg	Dc	Qty	Available	Descript
AD1981B	AD	N/a	684	avai	AD1981B AC'97 SoundMAX?Codec