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AD1959YRS-AD1959YRSRL
PLL/Multibit DAC
REV.0
PLL/Multibit �-� DAC
FUNCTIONAL BLOCK DIAGRAM
FEATURES
5 V Stereo Audio DAC System
Accepts 16-Bit/20-Bit/24-Bit Data
Supports 24 Bits, 192 kHz Sample Rate
Accepts a Wide Range of Sample Rates Including:
32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz
Multibit Sigma-Delta Modulator with Data Directed
Scrambling
Single-Ended Output for Easy Application
–94 dB THD + N
108 dB SNR and Dynamic Range
75 dB Stopband Attenuation
Clickless Volume Control
Hardware and Software Controllable Clickless Mute
Serial (SPI) Control for: Serial Mode, Number of Bits,
Sample Rate, Volume, Mute, De-Emphasis and
Output Phase
Digital De-Emphasis Processing for 32 kHz, 44.1 kHz,
and 48 kHz Sample Rates
Programmable Dual Fractional-N PLL Clock Generator
27 MHz Master Clock Input/Oscillator
Generated System Clocks
SCLK0: 33.8688 MHz
SCLK1: 384/256 fS (32 kHz/44.1 kHz/48 kHz/88.2 kHz/
96 kHz)
SCLK2: 512 fS (32 kHz/44.1 kHz/48 kHz/88.2 kHz/
96 kHz)/22.5792 MHz
Better than 100 ps RMS Clock Jitter
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S-Compatible, and DSP Serial Port Modes
28-Lead SSOP Plastic Package
APPLICATIONS
DVD, CD, Home Theater Systems, Automotive Audio
Systems, Sampling Musical Keyboards, Digital Mixing
Consoles, Digital Audio Effects Processors
PRODUCT OVERVIEWThe AD1959 is a complete high-performance single-chip stereo
digital audio playback system. It is comprised of a multibit sigma-
delta modulator, digital interpolation filters, and analog output
drive circuitry with an on-board dual PLL clock generator.
Other features include an on-chip stereo attenuator and mute,
programmed through an SPI-compatible serial control port.
The AD1959 is fully compatible with all known DVD formats
including 96 kHz and 192 kHz sample frequencies and 24 bits.
It also is backwards-compatible by supporting 50 µs/15 µs
digital de-emphasis for “redbook” compact discs, as well as
de-emphasis at 32 kHz and 48 kHz sample rates.
The AD1959 has a simple but flexible serial data input port that
allows for glueless interconnection to a variety of ADCs, DSP
chips, AES/EBU receivers, and sample rate converters. The
AD1959 can be configured in left-justified, I2S, right-justified,
or DSP serial-port-compatible modes. It can support 16, 20,
and 24 bits in all modes. The AD1959 accepts serial audio data
in MSB first, two’s-complement format, and operates from a
single 5 V power supply. It is fabricated on a single monolithic
integrated circuit and housed in a 28-lead SSOP package for
operation over the temperature range –40°C to +105°C.
AD1959–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTEDSupply Voltages (AVDD, DVDD)5.0 V
Ambient Temperature25°C
Input Clock12.288 MHz
Input Signal996.11 Hz
–0.5 dB Full Scale
Input Sample Rate48 kHz
Measurement Bandwidth20 Hz to 20 kHz
Word Width20 Bits
Load Capacitance100 pF
Load Impedance47 kΩ
Input Voltage HI3.5 V
Input Voltage LO0.8 V
ANALOG PERFORMANCEResolution
Signal-to-Noise Ratio (20 Hz to 20 kHz)
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
Total Harmonic Distortion + Noise (Stereo)
PLL Performance
Jitter (SCLK0 and SCLK1)
Analog Outputs
Interchannel Crosstalk (EIAJ Method)
Interchannel Phase Deviation
NOTES
Performance of right and left channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.
DIGITAL I/O (–40°C to +105°C )Input Voltage HI (VIH) Except XIN
Input Voltage HI (VIH) XIN
Input Voltage LO (VIL)
Input Leakage (IIL @ VIL = 0.8 V)
Low Level Output Voltage (VOL) IOL = 1 mA Except XOUT
Low Level Output Voltage (VOL) IOL = 1 mA XOUT
AD1959
TEMPERATURE RANGENOTES
*105°C ambient guaranteed for a 4-layer board, two 1 oz. planes, two 2 oz. signal layers. Derate to 85°C for 2-layer board, 2 oz. layers.
Specifications subject to change without notice.
POWERSpecifications subject to change without notice.
DIGITAL FILTER CHARACTERISTICSSpecifications subject to change without notice.
GROUP DELAYINT4× Mode
Specifications subject to change without notice.
DIGITAL TIMING (Guaranteed over –40°C to +105°C, AVDD = DVDD = 5.0 V ± 10%)
AD1959
ABSOLUTE MAXIMUM RATINGS*DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
Digital Inputs . . . . . . . . . . DGND – 0.3 V to DVDD + 0.3 V
Analog Inputs . . . . . . . . . . AGND – 0.3 V to AVDD + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to + 0.3 V
Reference Voltage . . . . . . . . . . . . . . . . . . . . . (AVDD + 0.3)/2
Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
PACKAGE CHARACTERISTICSθJA (Thermal Resistance) Junction-to-Ambient
109.0°C/W Typ (2-Layer Board)
θJA (Thermal Resistance) Junction-to-Ambient
78.58°C/W Typ (4-Layer Board—2 Signal, 2 Planes)
θJA (Thermal Resistance) Junction-to-Case
39.0°C/W Typ
ORDERING GUIDE
PIN CONFIGURATION
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1959 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS
AD1959
FUNCTIONAL DESCRIPTION
DACThe AD1959 has two DAC channels arranged as a stereo pair
with single-ended analog outputs. Each channel has its own
independently programmable attenuator, adjustable in 16384
linear steps. Digital inputs are supplied through a serial data input
pin, SDATA, a frame clock, LRCLK and a bit clock, BLCK.
Each analog output pin sits at a dc level of VREF, and swings
±1.585 V for a 0 dB digital input signal. A single op amp
third-order external low-pass filter is recommended to remove
high-frequency noise present on the output pins. The output
phase can be changed in an SPI control register to accommo-
date inverting and noninverting filters. Note that the use of op
amps with low slew rate or low bandwidth may cause high fre-
quency noise and tones to fold down into the audio band; care
should be exercised in selecting these components.
The FILTD and FILTR pins should be bypassed by external
capacitors to ground. The FILTD pin is used to reduce the noise
of the internal DAC bias circuitry, thereby reducing the DAC
output noise. The voltage at the VREF pin, FILTR (~2.39 V) can
be used to bias external op amps used to filter the output signals.
The DAC master clock frequency is 256 fS for the 32 kHz–48 kHz
range. For the 96 kHz range this is 128 fS. It is supplied inter-
nally from the PLL clock system when MCLK mode is set to
Output in the PLL Control Register. When the MCLK mode is
changed to Input, it must be supplied from an external source
connected to MCLK. The output from the 27 MHz PLL clock
is disabled in this case.
PLL Clock SystemThe PLL clock system operates from a 27 MHz master clock
supplied by the on-board crystal oscillator or an external source
connected to XIN. With the MCLK mode set to Output, the
27 MHz clock is buffered out to the MCLK pin. When set to
Input, the MCLK is the 256 fS master clock input for the DAC.
SCLK0 produces a 33.8688 MHz output, SCLK1 is intended
to be used as a master audio clock and will be a multiple of the
sample rate set in the PLL control register. It can be set to
256 fS or 384 fS using Bit 5 and to 512 fS or 768 fS, with Bit 4.
SCLK2 can be set to a constant 22.5792 MHz (512 × 44.1 kHz)
or 512 fS by Bit 3 of the PLL Control Register. Please note that
SCLK2 is intended to operate a DSP and does not meet the
jitter specifications stated under Analog Performance. All the
generated clocks can be set to 1/2 their nominal rate by setting
REF_Div2, Bit 8 in the PLL Control Register.
ResetRESET will set the control registers to their default settings. The
chip should be reset on power-up. After reset is deasserted, the
part will come out of reset on the next rising LRCLK.
Serial Control PortThe AD1959 has an SPI-compatible control port to permit
programming the internal control registers for the PLL and DAC.
The DAC output levels may be independently programmed
by means of an internal digital attenuator adjustable in 16384
linear steps.
The SPI control port is a 3-wire serial control port. The format
is similar to the Motorola SPI format except the input data word
is 16 bits wide. Max serial bit clock frequency is 8 MHz and
may be completely asynchronous to the PLL system or the
DAC. Figure 1 shows the format of the SPI signal. Note that the
CCLK can be gated or continuous, CLATCH should be low
during the 16 active clocks.
Figure 1.Format of SPI Signal
