AD1980JST ,AC ?7 SoundMAX CodecSPECIFICATIONSSTANDARD TEST CONDITIONS, UNLESS OTHERWISE DAC Test ConditionsNOTED CalibratedTempera ..
AD1980JST-REEL ,AC'97 SoundMAX® Codec w/SPDIF w/EQSPECIFICATIONSSTANDARD TEST CONDITIONS, UNLESS OTHERWISE DAC Test ConditionsNOTED CalibratedTempera ..
AD1980JST-REEL ,AC'97 SoundMAX® Codec w/SPDIF w/EQFEATURES Integrated Parametric Equalizer6 DAC Channels for 5.1 Surround Stereo MIC Preamp SupportS/ ..
AD1980JSTZ ,AC'97 SoundMAX® Codec w/SPDIF w/EQSPECIFICATIONSHigh Level Input Voltage (V ): Digital Inputs 0.65 DV VIH DDLow Level Input Voltage ..
AD1981AJST ,AC ?7 SoundMAX CodecSPECIFICATIONSSTANDARD TEST CONDITIONS UNLESS OTHERWISE NOTEDTemperature 25°C DAC Test ConditionsDi ..
AD1981B ,AD1981B AC'97 SoundMAX?CodecSPECIFICATIONSDAC Test ConditionsSTANDARD TEST CONDITIONS, UNLESSCalibratedOTHERWISE NOTED–3 dB Att ..
AD8381JST ,Fast, 6-Channel Output DecDriver™ Decimating LCD Panel DriverAPPLICATIONSLCD Analog Column Driver SCALINGCONTROLVREFHI VREFLO INV VMIDPRODUCT DESCRIPTIONThe AD8 ..
AD8381JST ,Fast, 6-Channel Output DecDriver™ Decimating LCD Panel DriverCHARACTERISTICSOutput Voltage Swing AVCC – VOH, VOL – AGND 1 1.3 V4CLK to VID Delay : t 50% of VIDx ..
AD8382ACP , High Performance 12-Bit, 6-Channel Output, Decimating LCD DecDriver
AD8382ACPZ ,High Performance 12-Bit, 6-Channel Output, Decimating LCD DecDriver®APPLICATIONS LCD analog column driver PRODUCT DESCRIPTION The AD8382 DecDriver provides a fast, 1 ..
AD8390A ,Low Power, High Output Current Differential AmplifierGENERAL DESCRIPTION PD1, providing three levels of driver bias and one power-down The AD8390A is a ..
AD8390ACP-REEL7 ,Low Power, High Output Current Differential AmplifierCHARACTERISTICS Differential Output Voltage Swing ∆V 43.8 44.2 44.6 V OUTOutput Balance Error ..
AD1953YST-AD1980JST
SigmaDSP⑩ 3-Channel, 26-Bit Signal Processing DAC
AC ’97 SoundMAXCodecREV.0
FEATURES
AC ’97 2.3 COMPATIBLE FEATURES
6 DAC Channels for 5.1 Surround
S/PDIF Output
Integrated Stereo Headphone Amplifier
Variable Rate Audio
Double Rate Audio (fS = 96 kHz)
Greater than 90 dB Dynamic Range
20-Bit PCM DACs
Line-Level Mono ”Phone” Input
High Quality CD Input
Selectable MIC Input with Preamp
AUX and Line_In Stereo Inputs
External Amplifier Power-Down Control
Power Management Modes
48-Lead LQFP Package
FUNCTIONAL BLOCK DIAGRAM
MC1
MC2
PHONE_IN
CD_L
CD_GND
CD_R
AUX_L
AUX_R
LINE_IN_L
VREF
VREFOUT
LINE_IN_R
XTL_OUTXTL_INSPDIF
ID0
ID1
RESET
SYNC
BITCLK
SDATA_OUT
SDATA_IN
JS0JS1EAPDLFE_OUTCENTER_OUTLINE_OUT_LMONO_OUTLINE_OUT_RSURR_OUT_L/
HP_OUT_LSURR_OUT_R/
HP_OUT_R
ENHANCED FEATURES
Integrated Parametric Equalizer
Stereo MIC Preamp Support
Integrated PLL for System Clocking
Variable Sample Rate 7 kHz to 96 kHz
Jack Sense (Auto Topology Switching)
Software Controlled VREF_OUT for MIC Bias
Software Enabled Outputs for Jack Sharing
Auto Down-Mix and Channel Spreading Modes
AD1980–SPECIFICATIONS
STANDARD TEST CONDITIONS, UNLESS OTHERWISE
NOTEDTemperature25°C
Digital Supply (DVDD)3.3 V
Analog Supply (AVDD)5.0 V
Sample Rate (fS)48 kHz
Input Signal1008 Hz
Analog Output Pass Band20 Hz to 20 kHz
DAC Test ConditionsCalibrated
–3 dB Attenuation Relative to Full Scale
0 dB Input
10 kΩ Output Load LINE_OUT, MONO_OUT,
CENTER_OUT, and LFE_OUT
32 Ω Output Load (HP_OUT)
ADC Test ConditionsCalibrated
0 dB Gain
Input –3.0 dB Relative to Full Scale
AD1980DIGITAL-TO-ANALOG CONVERTERS
ANALOG OUTPUT
AD1980NOTESPR bits are controlled in Reg. 2Ah and 26hValues presented with VREFOUT loaded.
Specifications subject to change without notice.
Setup to RESET Inactive (SYNC, SDATA_OUT)
TIMING PARAMETERS(Guaranteed over Operating Temperature Range)Guaranteed but not tested.
Specifications subject to change without notice.
Figure 1.Cold Reset Timing (Codec is Supplying the Bit_CLK Signal)
Figure 2.Warm Reset Timing
Figure 3.Clock Timing
Figure 4.Signal Rise and Fall Times
Figure 5.AC-Link Low Power Mode Timing
Figure 6.AC-Link Low Power Mode Timing
Figure 7.ATE Test Mode
AD1980
ABSOLUTE MAXIMUM RATINGS*Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Ambient Temperature (Operating)
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PIN CONFIGURATION
48-Lead LQFP
DVDD1
XTL_IN
XTL_OUT
DVSS1
SDATA_OUT
BIT_CLK
DVSS2
SDATA_IN
DVDD2
SYNC
RESET
LINE_OUT_R (FRONT_R)
LINE_OUT_L (FRONT_L)
AVDD4
AVSS4
LFE_OUT
CENTER_OUT
AFILT2
AFILT1
VREFOUT
VREF
AVSS1
AVDD1
SPDIFEAPDID1ID0AVSURR_OUT_R/HP_OUT_RAV
SURR_OUT_L/HP_OUT_LAV
MONO_OUT
ENVIRONMENTAL CONDITIONS*Ambient Temperature Rating
TCASE = Case Temperature in °C
PD = Power Dissipation in W
�JA = Thermal Resistance (Junction-to-Ambient)
�JC = Thermal Resistance (Junction-to-Case)
ORDERING GUIDE*ST = Low Profile Quad Flatpack
*All measurements per EIA/JESD51 with 2S2P
test board per EIA/JESD51-7.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD1980 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS6BIT_ CLK
JACK SENSE AND EAPD
AD19807DVSS2I
9DVDD2I
NO CONNECTS
Indexed Control Registers NOTES
All registers not shown and bits containing an X are assumed to be reserved.
Odd register addresses are aliased to the next lower even address.
Reserved registers should not be written to.
Zeros should be written to reserved bits.
AD1980
Master Volume Register (Index 02h)NOTESRefer to Table I for examples. This register controls the Line_Out volume controls for both stereo channels and mute bit. Each volume subregister contains five bits,
generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume registers, to maintain compatibility whenever the D5 or D13 bits are
set to “1,” their respective lower five volume bits are automatically set to “1” by the codec logic. On readback, all lower five bits will read “1s” whenever these bits are set
to “1.”For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved.
Note that depending on the state of the AC97NC bit in Register 0x76, this register has the following additional functionality:
For AC97NC = 0, the register controls the Line_out output Attenuators only.
For AC97NC = 1, the register controls the Line_out, Center, and LFE output Attenuators.
Reset Register (Index 00h)NOTES
All registers not shown and bits containing an X are assumed to be reserved.
Writing any value to this register performs a register reset, which causes all registers to revert to their default values (except 74h, which forces the serial configuration).
Reading this register returns the ID code of the part and a code for the type of 3D Stereo Enhancement.
ID[9:0] Identify Capability. The ID decodes the capabilities of AD1980 based on the following:
SE[4:0] Stereo Enhancement. The AD1980 does not provide hardware 3D stereo enhancement. (All bits are zeros.)
Table I.Volume Settings for Master and Headphone
Reg. 76h*For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, Bit D7 has no effect.
x in the above table is “don’t care.”
Mono Volume Register (Index 06h)*Refer to Table II for examples. This register controls the Mono output volume and mute bit. The volume register contains five bits, generating 32 volume levels with
31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume registers, to maintain compatibility, whenever the D5 bit is set to “1,” their respective lower five vol-
ume bits are automatically set to “1” by the codec logic. On readback, all lower five bits will read “1s” whenever this bit is set to “1.” All registers not shown and bits
containing an X are assumed to be reserved.
Table II.Volume Settings for Mono
Headphones Volume Register (Index 04h)*For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, Bit D7 has no effect.
AD1980
Phone_in Volume Register (Index 0Ch)All registers not shown and bits containing an X are assumed to be reserved. Refer to Table III for examples.
MIC Volume Register (Index 0Eh)All registers not shown, and bits containing an X are assumed to be reserved. Refer to Table III for examples.
Table III.Volume Settings for Phone and MICx in the above table is a wild card, and has no effect on the value.
CD Volume Register (Index 12h)*For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.
Line-In Volume Register (Index 10h)*For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.
AUX Volume Register (Index 16h)*For AC ’97 compatibility, Bit D7 is only available by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.
AD1980
PCM-Out Volume Register (Index 18h)*For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.
Note that depending on the state of the AC97NC bit in Register 76h, this register has the following additional functionality:
For AC87NC = 0, the register also controls the Surround, Center, and LFE DAC Gain/Attenuators.
For AC97NC = 1, the register controls the PCM Out Volume only.
Table IV.Volume Settings for Line-In, CD Volume, AUX, and PCM-Out*For AC ’97 compatibility, Bit D7 is only available by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, RM Bit has no effect.
x in the above table is “don’t care.”
Record Select Control Register (Index 1Ah)All registers not shown and bits containing an X are assumed to be reserved.
Refer to Table V for examples. Used to select the record source, independently for the right and left channels. For single MIC recording, see MS bit (Register 20h) for
MIC1 and MIC2 input selection.
For dual MIC recording, see 2CMIC bit (Register 76h) to enable simultaneous recording into the left and the right channels.
The default value is 0000h, which corresponds to MIC input for both channels.
Table V.Settings for Record Select Control
Table VI.Settings for Record Gain Register*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, Bit D7 has no effect.
x is “don’t care.”
Record Gain Register (Index 1Ch)*For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, Bit D7 has no effect. All registers not shown, and bits containing an X are assumed to be reserved. Refer to Table VI for examples.
AD1980
General-Purpose Register (Index 20h)This register should be read before writing to generate a mask for only the bit(s) that need to be changed. All registers not shown and bits containing an X are
assumed to be reserved.
Audio Interrupt and Paging Mechanism Register (Index 24h)This register controls the Audio Interrupt and Paging mechanism. All registers not shown and bits containing an X are assumed to be reserved.
