AD1940YSTZ ,SigmaDSP™ Multichannel 28-Bit Audio ProcessorSPECIFICATIONS Test conditions, unless otherwise noted. Table 1. Parameter Conditions Supply Volta ..
AD1953YST ,SigmaDSP⑩ 3-Channel, 26-Bit Signal Processing DACSPECIFICATIONSHigh Level Input Voltage (V ): Digital Inputs 0.65 DV VIH DDLow Level Input Voltage ..
AD1954YS ,SigmaDSP™ Digital Audio Processor with On-Board ConvertersOverview . . . . . . . . . . . . . . . . . . . . . . . . .12 SPI READ/WRITE DATA FORMATS . . . . ..
AD1954YST ,SigmaDSP 3-Channel/ 26-Bit Signal Processing DACSPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 SPI Address Dec ..
AD1955ARS ,High Performance, Multibit Sigma-Delta DAC with SACD PlaybackFEATURES FUNCTIONAL BLOCK DIAGRAM5 V Power Supply Stereo Audio DAC SystemDSDAccepts 16-/18-/20-/24- ..
AD1955ARSZ ,High Performance, Multibit Sigma-Delta DAC with SACD PlaybackSPECIFICATIONSTEST CONDITIONS(Unless otherwise noted.)Analog Supply Voltages (AV ) . . . . . . . . ..
AD8362ARU ,50 Hz to 2.7 GHz 60 dB TruPwr⑩ DetectorGENERAL DESCRIPTION The AD8362 is a true rms-responding power detector that has a the input power. ..
AD8362ARU-REEL7 ,50 Hz to 2.7 GHz 60 dB TruPwr⑩ DetectorSpecifications 3 Changes to the Offset Elimination Section..... 16 Effects at Each End of Dynamic R ..
AD8367ARU ,500 MHz, Linear-in-dB VGA with AGC DetectorSpecifications.Enable Input Bias Current ENBL at 5 V 27 AENBL at 0 V 32 nA–2– REV. 0AD8367Paramete ..
AD8367ARU-REEL7 ,500 MHz, Linear-in-dB VGA with AGC DetectorSPECIFICATIONS unless otherwise noted.)Parameter Conditions Min Typ Max UnitOVERALL FUNCTIONFrequen ..
AD8367ARUZ-RL7 , 500 MHz, Linear-in-dB VGA with AGC Detector
AD8369ARU ,45 dB Digitally Controlled VGA LF to 600 MHzAPPLICATIONSINHICellular/PCS Base StationsIF Sampling ReceiversCMDCFixed Wireless AccessINLOWirelin ..
AD1940YST-AD1940YSTZ
SigmaDSP™ Multichannel 28-Bit Audio Processor
SigmaDSPTM Multichannel
28-Bit Audio Processor
Rev. 0
FEATURES
16-channel digital audio processor
Accepts sample rates up to 192 kHz
28-bit × 28-bit multiplier with full 56-bit accumulator
Fully-programmable program RAM for custom
program download
Parameter RAM allows complete control of 1,024 parameters
Control port features safeload for transparent parameter
updates and complete mode and memory transfer control
Target/slew RAM for click-free volume control and dynamic
parameter updates
Double precision mode for full 56-bit processing
PLL for generating MCLK from 64 × fS, 256 × fS, 384 × fS, or
512 × fS clocks
Hardware-accelerated DSP core
21 kB (6,144 words) data memory for up to 128 ms of audio
delay at fs = 48 kHz
Flexible serial data port with I2S compatible, left-justified,
and right-justified serial port modes
8- and 16-channel TDM input/output modes
On-chip voltage regulator for compatibility with 3.3 V and
5 V systems
Programmable low power mode
Fast start-up and boot time from power on or reset
48-lead LQFP plastic package
APPLICATIONS
Automotive sound systems
Digital televisions
Home theater systems (Dolby Digital/DTS postprocessor)
Multichannel audio systems
Mini-component stereos
Multimedia audio
Digital speaker crossover
Musical instruments
In-seat sound systems (aircrafts/motor coaches)
FUNCTIONAL BLOCK DIAGRAM
SERIAL DATA/
TDM INPUTS
MASTER
CLOCK
INPUT
SPI I/O
SERIAL
DATA/
TDM
OUTPUTS04607-0-001Figure 1.
GENERAL DESCRIPTION The AD1940 is a complete 28-bit, single-chip, multichannel
audio DSP for equalization, multiband dynamics processing,
delay compensation, speaker compensation, and image
enhancement. These algorithms can be used to compensate for
the real-world limitations of speakers, amplifiers, and listening
environments, resulting in a dramatic improvement of
perceived audio quality.
The signal processing used in the AD1940 is comparable to that
found in high end studio equipment. Most of the processing is
done in full, 56-bit double-precision mode, resulting in very
good low level signal performance and the absence of limit
cycles or idle tones. The dynamics processor uses a sophisti-
cated, multiple-breakpoint algorithm often found in high end
broadcast compressors.
The AD1940 is a fully-programmable DSP. Easy to use software
allows the user to graphically configure a custom signal
processing flow using blocks such as biquad filters, dynamics
processors, and surround sound processors. An extensive
control port allows click-free parameter updates, along with
readback capability from any point in the algorithm flow.
The AD1940’s digital input and output ports allow a glueless
connection to ADCs and DACs by multiple, 2-channel serial
data streams or TDM data streams. When in TDM mode, the
AD1940 can input 8 or 16 channels of serial data, and can
output either 8 or 16 channels of serial data. The input and
output port configurations can be individually set. The AD1940
is controlled via a 4-wire SPI port.
TABLE OF CONTENTS Specifications.....................................................................................3
Digital I/O.....................................................................................3
Power..............................................................................................3
Temperature Range......................................................................3
Digital Timing...............................................................................4
PLL.................................................................................................4
Regulator........................................................................................4
Absolute Maximum Ratings............................................................5
ESD Caution..................................................................................5
Digital Timing Diagrams.................................................................6
Pin Configuration and Function Descriptions.............................8
Features............................................................................................10
Pin Functions..............................................................................11
Signal Processing............................................................................13
Overview......................................................................................13
Numeric Formats........................................................................13
Programming..............................................................................13
Control Port.....................................................................................14
Overview......................................................................................14
RAMs and Registers.......................................................................16
Control Port Addressing............................................................16
Parameter RAM Contents.........................................................16
Recommended Program/Parameter Loading Procedures....17
Target/Slew RAM.......................................................................17
Safeload Registers.......................................................................19
Data Capture Registers..............................................................20
DSP Core Control Register.......................................................20
RAM Configuration Register...................................................21
Control Port Read/Write Data Formats..................................22
Serial Data Input/Output Ports....................................................24
Serial Output Control Registers...............................................26
Serial Input Control Register....................................................26
Initialization....................................................................................29
Power-Up Sequence...................................................................29
Setting Master Clock/PLL Mode..............................................29
Voltage Regulator.......................................................................29
Outline Dimensions.......................................................................30
Ordering Guide..........................................................................30
REVISION HISTORY
7/04—Revision 0: Initial Version
SPECIFICATIONS Test conditions, unless otherwise noted.
Table 1.
DIGITAL I/O
Table 2. Digital I/O1 1 All measurements across −40°C to 125°C (case) and across VDD = 2.25 V to 2.75 V.
POWER
Table 3. 1 Maximum specifications are measured across −40°C to 125°C (case) and across VDD = 2.25 V to 2.75 V. Measurement running a typical large program that writes to all 16 outputs with 0 dB digital sine waves applied to all eight inputs. Your program may differ.
3 The digital reset current is specified for the given test conditions. This current scales with the input MCLK rate, so higher input clocks draw more current while in reset.
TEMPERATURE RANGE
Table 4.
DIGITAL TIMING
Table 5 Digital Timing1 All timing specifications are given for the default (I2S) states of the serial input control port and the serial output control ports. See. Table 32
2 These specifications are based on the internal master clock period in a specific application. In normal operation, the master clock runs at 1,536 × fs, so the internal master
clock at fs = 48 kHz has a 14 ns period. The values in parentheses are the timing values for fs = 48 kHz.
PLL
Table 6.
REGULATOR
Table 7. ABSOLUTE MAXIMUM RATINGS
Table 8. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 9. Package Characteristics
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
DIGITAL TIMING DIAGRAMS
BCLK_IN
LRCLK_IN
SDATA_INX
LEFT-JUSTIFIED
MODE
SDATA_INX
I2S-JUSTIFIED
MODE
SDATA_INX
RIGHT-JUSTIFIED
MODE
tBIH
16-BIT CLOCKS
(16-BIT DATA)04607-0-013 Figure 2. Serial Input Port Timing
BCLK_OUTX
LRCLK_OUTX
SDATA_OUTX
LEFT-JUSTIFIED
MODE
SDATA_OUTX
I2S-JUSTIFIED
MODE
SDATA_OUTX
RIGHT-JUSTIFIED
MODE
tBIH
16-BIT CLOCKS
(16-BIT DATA)04607-0-014
CLATCH
CCLK
CDATA
COUT
tCDS
tCDH
tCOD04607-0-015 Figure 4. SPI Port Timing
MCLK
RESETB04607-0-016 Figure 5. Master Clock and Reset Timing
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
BCLK_OUT1
LRCLK_OUT1
ODVDD
SDATA_OUT3
SDATA_OUT2
SDATA_OUT1
VDD
MCLK
RESERVED
PLL_VDD
SDATA_OUT0
ODVDD
BCLK_OUT0
LRCLK_OUT0
GNDVDD
PLL_CTRL0
PLL_CTRL1
PLL_CTRL2
PLL_GND
DATA_
IN0
ADR_
SEN
PPLY
TA_OUT6
TA_OUT5
_OULRCLK_IN
BCLK_IN
NC = NO CONNECT Figure 6. 48-Lead LQFP Pin Configuration
Table 10. Pin Function Descriptions
FEATURES
The core of the AD1940 is a 28-bit DSP (56-bit with double
precision) optimized for audio processing.
The AD1940 contains a program RAM that is initialized from
an internal program ROM on power-up. The program RAM
can be loaded with a custom program after power-up. Signal
processing parameters are stored in a 1024-location parameter
RAM, which is initialized on power-up by an internal boot-
ROM. New values are written to the parameter RAM using the
control port. The values stored in the parameter RAM control
individual signal processing blocks, such as IIR equalization
filters, dynamics processors, audio delays, and mixer levels. A
safeload feature allows parameters to be transparently updated
without causing clicks on the output signals.
The target/slew RAM contains 64 locations and can be used as
channel volume controls or for other parameter updates. These
RAM locations take a target value for a given parameter and
ramp the current parameter value to the new value using a
specified time constant and one of a selection of linear or
logarithmic curves.
The AD1940 has a sophisticated control port that supports
complete read/write capability of all memory locations. Five
control registers (core, RAM configuration, Serial Output 0 to 7,
Serial Output 8 to 15, and serial input) are provided to offer
complete control of the chip’s configuration and serial
modes. Handshaking is included for ease of memory
uploads/downloads.
The AD1940 contains eight independent data capture circuits
that can be programmed to tap the signal flow of the processor
at any point in the DSP algorithm flow. Six of these captured
signals can be accessed by reading from the data capture
registers through the control port. The remaining two data
capture registers can be used to send any internal captured
signal to a stereo digital output signal on Pin SDATA_OUT7 for
driving external DACs or digital analyzers.
The AD1940 has very flexible serial data input/output ports that
allows for glueless interconnection to a variety of ADCs, DACs,
general-purpose DSPs, S/PDIF receivers, and sample rate
converters. The AD1940 can be configured in I2S, left-justified,
right-justified, or TDM serial port compatible modes. It can
support 16, 20, and 24 bits in all modes. The AD1940 accepts
serial audio data in MSB first and twos complement format.
The AD1940 operates from a single 2.5 V power supply. It is
fabricated on a single monolithic integrated circuit and is
housed in a 48-lead LQFP package for operation over the
–40°C to +105°C temperature range.
04607-0-003SERIAL
INPUT
GROUP
PLL MODE
SELECT
MASTER
CLOCK
INPUT
SPI I/O
GROUP
RESETB
SERIAL DATA/
TDM OUTPUT
GROUP
REGULATOR
GROUPFigure 7. Block Diagram
PIN FUNCTIONS
Table 10 shows the AD1940’s pin numbers, names, and
functions. Input pins have a logic threshold compatible with
TTL input levels and may be used in systems with 3.3 V or
5 V logic.
SDATA_IN0
SDATA_IN1
SDATA_IN2/TDM_IN1
SDATA_IN3/TDM_IN0
Serial Data/TDM Inputs. The serial format is selected by writing
to Bits 2:0 of the serial input port control register. SDATA_IN2
and SDATA_IN3 are dual-function pins that can be set to a
variety of standard 2-channel formats or to TDM mode. Two of
these four pins (SDATA_IN2 and SDATA_IN3) can be used as
TDM inputs in either dual-wire 8-channel mode or single-wire
16-channel mode (TDM_O0 only). In dual-wire 8-channel
mode, Channels 0-7 will be input on SDATA_IN3 and
Channels 8-15 on SDATA_IN2. In single-wire 16-channel
mode, Channels 0-15 will be input on SDATA_IN2. See the
Serial Data Input/Output Ports section for further explanation.
LRCLK_IN
BCLK_IN
Left/Right and Bit Clocks for Timing the Input Data. These
input clocks are associated with the SDATA_IN0-3 signals. The
input port is always in a slave configuration. These pins also
function as frame sync and bit clock for the input TDM stream.
SDATA_OUT0/TDM_O0
SDATA_OUT1
SDATA_OUT2,
SDATA_OUT3
SDATA_OUT4/TDM_O1
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7/DCSOUT
Serial Data/TDM/Data Capture Outputs. These pins are used
for serial digital outputs. For non-TDM systems, these eight
pins can output 16 channels of digital audio, using a variety of
standard two-channel formats. They are grouped into two
groups of four pins (0-3 and 4-7); each group can be indepen-
dently set to any of the available serial modes, allowing the
AD1940 to simultaneously communicate with two external
devices with different serial formats. Two of these eight pins
(SDATA_OUT0 and SDATA_OUT4) can be used as TDM
outputs in either dual-wire 8-channel mode or single-wire
16-channel mode (TDM_OUT0 only). In dual-wire 8-channel
mode, Channels 0-7 will be output on SDATA_OUT0 and
Channels 8-15 on SDATA_OUT4. See the Serial Data
Input/Output Ports section for further explanation.
SDATA_OUT7 can also be used as a data capture output, as
described in the Data Capture Registers section.
LRCLK_OUT0
BCLK_OUT0
Output Clocks. This clock pair is used for outputs
SDATA_OUT0–3. In slave mode, these clocks are inputs
to the AD1940. On power-up, these pins are set to slave
mode to avoid conflicts with external master-mode devices.
LRCLK_OUT1
BCLK_OUT1
Output Clocks. This clock pair is used for outputs
SDATA_OUT4–7. In slave mode, these clocks are inputs
to the AD1940. On power-up, these pins are set to slave
mode to avoid conflicts with external master-mode devices.
MCLK
Master Clock Input. The AD1940 uses a PLL to generate the
appropriate internal clock for the DSP core. An in-depth
description of using the PLL is found in the Setting Master
Clock/PLL Mode section.
PLL_CTRL0
PLL_CTRL1
PLL_CTRL2
PLL Mode Control Pins. The functionality of these pins is
described in the Setting Master Clock/PLL Mode section.
CDATA
Serial Data Input for the SPI Control Port.
COUT
Serial Data Output for the SPI Port. This is used for reading
back registers and memory locations. It is three-stated when an
SPI read is not active.
CCLK
SPI Bit Clock. This clock may either run continuously or be
gated off in between SPI transactions.
CLATCH
SPI Latch Signal. This must go low at the beginning of an SPI
transaction and high at the end of a transaction. Each SPI
transaction may take a different number of CCLKs to complete,
depending on the address and read/write bit that are sent at the
beginning of the SPI transaction.
ADR_SEL
Address Select. This pin selects the address for the AD1940’s
communication with the control port. This allows two AD1940s
to be used with a single CLATCH signal.
RESETB
Active-Low Reset Signal. After RESETB goes high, the AD1940
goes through an initialization sequence where the program and
parameter RAMs are initialized with the contents of the on-
board boot ROMs. All registers are set to 0, and the data
RAMs are also set to 0. The initialization is complete after
8,192 internal MCLK cycles (referenced to the rising edge of
RESETB), which corresponds to 1,366 external MCLK cycles if
the part is in 256 × fS mode. New values should not be written to
the control port until the initialization is complete.
VREF
Voltage Reference for Regulator. This pin is driven by an
internal 1.15 V reference voltage.
VDRIVE
Drive for External Transistor. The base of the voltage regulator’s
external PNP transistor is driven from this pin.
VSENSE
Digital power level. The voltage level on the VDD pins is sensed
on VSENSE. VSENSE should be tied to VDD.
VSUPPLY
Main Supply Voltage Level. This pin is tied to the board’s main
voltage supply. This is usually 3.3 V or 5 V.
VDD (4)
Digital VDD for Core. 2.5 V nominal.
GND (4)
Digital Ground.
PLL_VDD
Supply for AD1940 PLL. 2.5 V nominal.
PLL_GND
PLL Ground.
ODVDD (3)
VDD for All Digital Outputs. The high levels of the digital
output signals are set on this pin. The voltage can range from
2.5 V to 5.0 V.
INVDD
Peak Input Voltage Level. The highest voltage level that the
input pins will see should be connected to INVDD. This is to
protect the chip inputs from voltage overstress. The voltage on
this pin must always be at or above the level of ODVDD.
SIGNAL PROCESSING
OVERVIEW
The AD1940 is designed to provide all signal processing
functions commonly used in stereo or multichannel playback
systems. The signal processing flow is set by using the ADI-
supplied software, which allows graphical entry and real-time
control of all signal processing functions.
Many of the signal processing functions are coded using full,
56-bit double-precision arithmetic. The input and output word
lengths are 24 bits. Four extra headroom bits are used in the
processor to allow internal gains up to 24 dB without clipping.
Additional gains can be achieved by initially scaling down the
input signal in the signal flow.
The signal processing blocks can be arranged in a custom pro-
gram that can be loaded to the AD1940’s RAM. The available
signal processing blocks are explained in the following sections.
NUMERIC FORMATS
It is common in DSP systems to use a standardized method of
specifying numeric formats. Fractional number systems are
specified by an A.B format, where A is the number of bits to the
left of the decimal point and B is the number of bits to the right
of the decimal point.
The AD1940 uses the same numeric format for both the coeffi-
cient values (stored in the parameter RAM) and the signal data
values. The format is as follows:
Numerical Format: 5.23
Range: –16.0 to (+16.0 − 1 LSB)
Examples:
1000000000000000000000000000 = –16.0
1110000000000000000000000000 = –4.0
1111100000000000000000000000 = –1.0
1111111000000000000000000000 = –0.25
1111111111111111111111111111 = (1 LSB below 0.0)
0000000000000000000000000000 = 0.0
0000001000000000000000000000 = 0.25
0000100000000000000000000000 = 1.0
0010000000000000000000000000 = 4.0
0111111111111111111111111111 = (16.0 – 1 LSB).
The serial port accepts up to 24 bits on the input and is sign-
extended to the full 28 bits of the core. This allows internal
gains of up to 24 dB without encountering internal clipping.
A digital clipper circuit is used between the output of the DSP
core and the serial output ports (see Figure 8). This clips the top
four bits of the signal to produce a 24-bit output with a range of
1.0 (minus 1 LSB) to –1.0.
4-BIT SIGN EXTENSION
DATA IN
1.235.231.23
04607-0-005 Figure 8. Numeric Precision and Clipping Structure
PROGRAMMING
On power-up, the AD1940’s default program passes the unpro-
cessed input signals to the outputs but the outputs come up
muted by default (see Power-Up Sequence section). There are
1,536 instruction cycles per audio sample, resulting in an inter-
nal clock rate of 73.728 MHz (for fs = 48 kHz). This DSP runs in
a stream-oriented manner, meaning all 1,536 instructions are
executed each sample period. The AD1940 may also be set
up to accept double or quad-speed inputs by reducing the
number of instructions/sample, which can be set in the core
control register.
The part can be programmed easily using graphical tools pro-
vided by Analog Devices. No knowledge of writing DSP code is
needed to program this part. The user can simply connect
graphical blocks such as biquad filters, dynamics processors,
mixers, and delays in a signal flow schematic, compile the
design, and load the program and parameter files into the
AD1940’s Program RAM through the control port. Signal
processing blocks available in the provided libraries include Single- and double-precision biquad filters Mono and multichannel dynamics processors Mixers and splitters Tone and noise generators First-order filters Fixed and variable gain RMS look-up tables Loudness Delay Stereo enhancement (Phat Stereo™) Interpolators and Decimators
More blocks are always in development. Analog Devices also
provides proprietary and third-party algorithms for applications
such as matrix decoding, bass enhancement, and surround
virtualizers. Please contact ADI for information about licensing
these algorithms.
CONTROL PORT
OVERVIEW
The AD1940 has many different control options that can be set
through an SPI interface. Most signal processing parameters are
controlled by writing new values to the parameter RAM using
the control port. Other functions, such as mute and input/
output mode control, are programmed by writing to the
control registers.
The control port is capable of full read/write operation for all of
the memories and registers. All addresses may be accessed in
both a single-address mode or a burst mode. A control word
consists of the chip address, the register/RAM subaddress, and
the data to be written. The data can be variable in its byte width.
The first byte of a control word (Byte 0) contains the 7-bit chip
address plus the R/W bit. The next two bytes (Bytes 1 and 2)
together form the subaddress of the memory or register
location within the AD1940. This subaddress needs to be two
bytes because the memories within the AD1940 are directly
addressable, and their sizes exceed the range of single-byte
addressing. All subsequent bytes (Bytes 3, 4, etc.) contain the
data, such as control port data or program or parameter data.
The AD1940 has several mechanisms for updating signal
processing parameters in real time without causing pops or
clicks. In cases where large blocks of data need to be down-
loaded, the output of the DSP core can be halted (using Bit 9 of
the core control register), new data loaded, and then restarted.
This is typically done during the booting sequence at start-up or
when loading a new program into RAM. In cases where only a
few parameters need to be changed, they can be loaded without
halting the program. To avoid unwanted side effects while
loading parameters on the fly, the SigmaDSP provides the
safeload registers. The safeload registers can be used to buffer a
full set of parameters (e.g. the five coefficients of a biquad) and
then transfer these parameters into the active program within
one audio frame. The safeload mode uses internal logic to
prevent contention between the DSP core and the control port.
The SPI port uses a 4-wire interface, consisting of CLATCH,
CCLK, CDATA, and COUT signals. The CLATCH signal goes
low at the beginning of a transaction and high at the end of a
transaction. The CCLK signal latches CDATA on a low-to-high
transition. COUT data is shifted out of the AD1940 on the
falling edge of CCLK and should be clocked into the receiving
device, such as a microcontroller, on CCLK’s rising edge. The
CDATA signal carries the serial input data, and the COUT
signal is the serial output data. The COUT signal remains three-
stated until a read operation is requested. This allows other SPI-
compatible peripherals to share the same readback line. All SPI
transactions follow the same basic format, shown in Table 11. A
timing diagram is shown in Figure 4. All data written should be
MSB-first.
Table 11. Generic SPI Word Format
Chip Address R/W
The first byte of an SPI transaction includes the 7-bit chip
address and a R/W bit. The chip address is set by the ADR_SEL
pin. This allows two AD1940s to share a CLATCH signal, yet
still operate independently. When ADR_SEL is low, the chip
address is 0000000; when it is high, the address is 0000001. The
LSB of this first byte determines whether the SPI transaction is
a read (Logic Level 1) or a write (Logic Level 0).
RAM/Register Address
The 12-bit RAM/register address word is decoded into a
location in one of the memories or registers.
Data Bytes
The number of data bytes varies according to the register or
memory being accessed. In burst write mode, an initial address
is given followed by a continuous sequence of data for
consecutive memory/register locations. The detailed data
format diagram for continuous-mode operation is given in the
Control Port Read/Write Data Formats section.
A sample timing diagram for a single SPI write operation to the
parameter RAM is shown in Figure 9. A sample timing diagram
of a single SPI read operation is shown in Figure 10. The COUT
pin goes from three-state to driven at the beginning of Byte 3.
In this example, Bytes 0 to 2 contain the addresses and R/W bit,
and subsequent bytes carry the data. The exact formats for
specific types of writes are shown in Table 21 to Table 30.
CLATCH
CCLK
CDATA
04607-0-006 Figure 9. Sample of SPI WRITE format (Single-Write Mode)
CLATCH
CCLK
CDATA
COUTFigure 10. Sample of SPI READ Format (Single-Read Mode)
RAMS AND REGISTERS
Table 12. Control Port Addresses
Table 13. RAM Read/Write Modes 1 DSP core should be shut down first to avoid clicks/pops. The target/slew RAMs need to be written through the safeload registers. Safeload writes may be done in either single-write or burst-mode.
CONTROL PORT ADDRESSING Table 12 shows the addressing of the AD1940’s RAM and
register spaces. The address space encompasses a set of registers
and three RAMs: one each for holding signal processing
parameters, holding the program instructions, and ramping
parameter values. The program and parameter RAMs are
initialized on power-up from on-board boot ROMs.
Table 13 shows the sizes and available writing modes of the
parameter, program, and target/slew RAMs.
PARAMETER RAM CONTENTS The parameter RAM is 28 bits wide and occupies Addresses 0 to
1023. The parameter RAM is initialized to all 0s on power-up.
The data format of the parameter RAM is twos complement
5.23. This means that the coefficients may range from +16.0
(minus 1 LSB) to –16.0, with 1.0 represented by the binary word
0000100000000000000000000000.
Options for Parameter Updates The parameter RAM can be written and read using one of the
two following methods.
1.
Direct Read/Write. This method allows direct access to the program and parameter RAMs. This mode of operation is
normally used during a complete new load of the RAMs,
using burst-mode addressing. The clear registers bit in the
core control register should be set to 0 using this mode to
avoid any clicks or pops in the outputs. Note that it is also
possible to use this mode during live program execution,
but since there is no handshaking between the core and the
control port, the parameter RAM will be unavailable to the
DSP core during control writes, resulting in clicks and pops
in the audio stream.
2.
Safeload Writes. Up to five safeload registers can be loaded with address/data intended for the parameter RAM. The
data is then transferred to the requested address when the
RAM is not busy. This method can be used for dynamic
updates while live program material is playing through the
AD1940/AD1941. For example, a complete update of one
biquad section can occur in one audio frame, while the
RAM is not busy. This method is not available for writing
to the program RAM or control registers.
