AD1896AYRSRL ,192 kHz Stereo Asynchronous Sample Rate Converterfeatures include more serialpolyphases, a FIFO, a digital servo loop that measures the timeformats, ..
AD1896AYRSZ ,192 kHz Stereo Asynchronous Sample Rate ConverterSpecifications subject to change without notice.DIGITAL PERFORMANCE (VDD_CORE = 3.3 V 5%, VDD_IO ..
AD1896YRS ,192 kHz Stereo Asynchronous Sample Rate ConverterSpecifications subject to change without notice.–2– REV. 0AD1896DIGITAL TIMING (–40C < T < +105C, ..
AD1896YRSRL ,192 kHz Stereo Asynchronous Sample Rate ConverterSpecifications subject to change without notice.DIGITAL PERFORMANCE (VDD_CORE = 3.3 V 5%, VDD_IO ..
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AD8361ARM. ,LF to 2.5 GHz TruPwr⑩ DetectorAPPLICATIONSMeasurement of CDMA, W-CDMA, QAM, OtherADDOFFSETComplex Modulation WaveformsBAND-GAPSRE ..
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AD8361ARMZ-REEL , LF to 2.5 GHz TruPwr™ Detector
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AD1896AYRS-AD1896AYRSRL-AD1896AYRSZ
192 kHz Stereo Asynchronous Sample Rate Converter
REV.A
192 kHz Stereo Asynchronous
Sample Rate Converter
FUNCTIONAL BLOCK DIAGRAM
GRPDLYSVDD_IOVDD_CORE
BYPASS
MUTE_O
MUTE_I
SDATA_I
SCLK_I
LRCLK_I
SMODE_IN_0
SMODE_IN_1
SMODE_IN_2
MCLK_I
MCLK_O
MSMODE_1
WLNGTH_O_0
WLNGTH_O_1
SMODE_O_0
SMODE_O_1
TDM_IN
SDATA_O
SCLK_O
LRCLK_O
RESET
PRODUCT OVERVIEWThe AD1896 is a 24-bit, high performance, single-chip, second-
generation asynchronous sample rate converter. Based on Analog
Devices experience with its first asynchronous sample rate
converter, the AD1890, the AD1896 offers improved performance
and additional features. This improved performance includes a
THD + N range of –117 dB to –133 dB depending on the sample
rate and input frequency, 142 dB (A-Weighted) dynamic range,
192 kHz sampling frequencies for both input and output sample
rates, improved jitter rejection, and 1:8 upsampling and 7.75:1
downsampling ratios. Additional features include more serial
formats, a bypass mode, better interfacing to digital signal pro-
cessors, and a matched-phase mode.
The AD1896 has a 3-wire interface for the serial input and
output ports that supports left-justified, I2S, and right-justified
(16-, 18-, 20-, 24-bit) modes. Additionally, the serial output
port supports TDM mode for daisy-chaining multiple AD1896s to
a digital signal processor. The serial output data is dithered down
to 20, 18, or 16 bits when 20-, 18-, or 16-bit output data is se-
lected. The AD1896 sample rate converts the data from the
serial input port to the sample rate of the serial output port. The
sample rate at the serial input port can be asynchronous with
respect to the output sample rate of the output serial port. The
master clock to the AD1896, MCLK, can be asynchronous to
both the serial input and output ports.
MCLK can be generated either off-chip or on-chip by the AD1896
master clock oscillator. Since MCLK can be asynchronous to the
input or output serial ports, a crystal can be used to generate
MCLK internally to reduce noise and EMI emissions on the
board. When MCLK is synchronous to either the output or input
serial port, the AD1896 can be configured in a master mode where
MCLK is divided down and used to generate the left/right
and bit clocks for the serial port that is synchronous to MCLK.
The AD1896 supports master modes of 256 ¥ fS, 512 ¥ fS,
and 768 ¥ fS for both input and output serial ports.
Conceptually, the AD1896 interpolates the serial input data by
a rate of 220 and samples the interpolated data stream by the
output sample rate. In practice, a 64-tap FIR filter with 220
polyphases, a FIFO, a digital servo loop that measures the time
difference between the input and output samples within 5 ps,
and a digital circuit to track the sample rate ratio are used to
perform the interpolation and output sampling. Refer to the
Theory of Operation section. The digital servo loop and sample
rate ratio circuit automatically track the input and output
sample rates.
(Continued on Page 17)
FEATURES
Automatically Senses Sample Frequencies
No Programming Required
Attenuates Sample Clock Jitter
3.3 V–5 V Input and 3.3 V Core Supply Voltages
Accepts 16-/18-/20-/24-Bit Data
Up to 192 kHz Sample Rate
Input/Output Sample Ratios from 7.75:1 to 1:8
Bypass Mode
Multiple AD1896 TDM Daisy-Chain Mode
Multiple AD1896 Matched-Phase Mode
142 dB Signal-to-Noise and Dynamic Range
(A-Weighted, 20 Hz–20 kHz BW)
Up to –133 dB THD + N
Linear Phase FIR Filter
Hardware Controllable Soft Mute
Supports 256 � fS, 512 � fS, or 768 � fS Master
Mode Clock
Flexible 3-Wire Serial Data Port with Left-Justified,2S, Right-Justified (16-,18-, 20-, 24-Bits), and
TDM Serial Port Modes
Master/Slave Input and Output Modes
28-Lead SSOP Plastic Package
APPLICATIONS
Home Theater Systems, Studio Digital Mixers,
Automotive Audio Systems, DVD, Set-Top Boxes,
Digital Audio Effects Processors, Studio-to-Transmitter
Links, Digital Audio Broadcast Equipment,
DigitalTape Varispeed Applications*Patents pending.
AD1896–SPECIFICATIONS
TEST CONDITIONS, UNLESS OTHERWISE NOTED.Supply Voltages
VDD_CORE3.3 V
VDD_IO5.0 V or 3.3 V
Ambient Temperature25°C
Input Clock30.0 MHz
Input Signal1.000 kHz, 0 dBFS
Measurement Bandwidth20 to fS_OUT/2 Hz
Word Width24 Bits
Load Capacitance50 pF
Input Voltage High2.4 V
Input Voltage Low0.8 V
Specifications subject to change without notice.
DIGITAL PERFORMANCE (VDD_CORE = 3.3 V � 5%, VDD_IO = 5.0 V � 10%)Sample Rate Ratios
Dynamic Range
NOTESLower sampling rates than given by this formula are possible, but the jitter rejection will decrease.Refer to the Typical Performance Characteristics section for DNR and THD + N numbers over wide range of input and output sample rates.For any other sample rate ratio, the minimum THD + N will be better than –117 dB. Please refer to detailed performance plots.
Specifications subject to change without notice.
AD1896
DIGITAL TIMING (–40�C < TA < +105�C, VDD_CORE = 3.3 V � 5%, VDD_IO = 5.0 V � 10%)NOTESRefer to Timing Diagrams section.The maximum possible sample rate is: FSMAX = fMCLK/138.fMCLK of up to 34 MHz is possible under the following conditions: 0∞C < TA < 70∞C, 45/55 or better MCLK_I duty cycle.
Specifications subject to change without notice.
AD1896
TIMING DIAGRAMSFigure 1.Input and Output Serial Port Timing (SCLK I/O,
LRCLK I/O, SDATA I/O, TDM_IN)
Figure 2.RESET Timing
Figure 3.MCLK_I Timing
AD1896
DIGITAL FILTERS (VDD_CORE = 3.3 V � 5%, VDD_IO = 5.0 V � 10%)Pass-Band Ripple
Transition Band
Stop-Band
Stop-Band Attenuation
Specifications subject to change without notice.
DIGITAL I/O CHARACTERISTICS (VDD_CORE = 3.3 V � 5%, VDD_IO = 5.0 V � 10%)Input Voltage Low (VIL)
Input Leakage (IIH @ VIH = 5 V)
Output Source Current High (IOH)–4
NOTESAll input pins except GRPDLYS.GRPDLYS pin only.
Specifications subject to change without notice.
POWER SUPPLIESActive Supply Current
Power-Down Supply Current: (All Clocks Stopped)
*For 3.3 V tolerant inputs, VDD_IO supply should be set to 3.3 V; however, VDD_CORE supply voltage should not exceed VDD_IO.
Specifications subject to change without notice.
