AD1895AYRSZ ,192 kHZ Stereo Asynchronous Sample Rate Converterfeatures include 20output sample rate. In practice, a 64-tap FIR filter with 2more serial formats, ..
AD1895YRS ,192 kHz Stereo Asynchronous Sample Rate ConverterFEATURESAutomatically Senses Sample FrequenciesVDD_IO VDD_CORERESETNo Programming RequiredAttenuate ..
AD1895YRSRL ,192 kHz Stereo Asynchronous Sample Rate ConverterSpecifications subject to change without notice.DIGITAL PERFORMANCE (VDD_CORE = 3.3 V 5%, VDD_IO ..
AD1896AYRS ,192 kHz Stereo Asynchronous Sample Rate ConverterSpecifications subject to change without notice.–2– REV. AAD1896DIGITAL TIMING (–40C < T < +105C, ..
AD1896AYRSRL ,192 kHz Stereo Asynchronous Sample Rate Converterfeatures include more serialpolyphases, a FIFO, a digital servo loop that measures the timeformats, ..
AD1896AYRSZ ,192 kHz Stereo Asynchronous Sample Rate ConverterSpecifications subject to change without notice.DIGITAL PERFORMANCE (VDD_CORE = 3.3 V 5%, VDD_IO ..
AD835AR ,250 MHz, Voltage Output 4-Quadrant MultiplierSpecifications subject to change without notice.–2– REV. AAD8351PIN CONNECTIONSABSOLUTE MAXIMUM RAT ..
AD8361 ,2.5 GHz TruPwr?DetectorApplications section.5SOT-23-6L operates in ground reference mode only.6The available output swing, ..
AD8361ARM ,LF to 2.5 GHz TruPwr⑩ DetectorLF to 2.5 GHz™aTruPwr DetectorAD8361
AD8361ARM. ,LF to 2.5 GHz TruPwr⑩ DetectorAPPLICATIONSMeasurement of CDMA, W-CDMA, QAM, OtherADDOFFSETComplex Modulation WaveformsBAND-GAPSRE ..
AD8361ARM-REEL ,LF to 2.5 GHz TruPwr⑩ DetectorApplications section.5SOT-23-6L operates in ground reference mode only.6The available output swing, ..
AD8361ARM-REEL7 ,LF to 2.5 GHz TruPwr⑩ DetectorFEATURES FUNCTIONAL BLOCK DIAGRAMSCalibrated RMS ResponseExcellent Temperature Stability micro_SOIC ..
AD1895AYRS-AD1895AYRSRL-AD1895AYRSZ
192 kHZ Stereo Asynchronous Sample Rate Converter
REV. B
192 kHz Stereo Asynchronous
Sample Rate Converter
FUNCTIONAL BLOCK DIAGRAM
VDD_IOVDD_CORE
AD1895
BYPASS
MUTE_OUT
MUTE_IN
SDATA_I
SCLK_I
LRCLK_I
SMODE_IN_0
SMODE_IN_1
SMODE_IN_2
MCLK_IN
MCLK_OUT
MMODE_1
WLNGTH_OUT_0
WLNGTH_OUT_1
SMODE_OUT_0
SMODE_OUT_1
TDM_IN
SDATA_O
SCLK_O
LRCLK_O
RESET
PRODUCT OVERVIEWThe AD1895 is a 24-bit, high performance, single-chip, second
generation asynchronous sample rate converter. Based upon
Analog Devices’ experience with its first asynchronous sample
rate converter, the AD1890, the AD1895 offers improved perfor-
mance and additional features. This improved performance
includes a THD + N range of –115 dB to –122 dB depending
on sample rate and input frequency, 128 dB (A-Weighted)
dynamic range, 192 kHz sampling frequencies for both input and
output sample rates, improved jitter rejection, and 1:8 upsampling
and 7.75:1 downsampling ratios. Additional features include
more serial formats, a bypass mode, and better interfacing to
digital signal processors.
The AD1895 has a 3-wire interface for the serial input and
output ports that supports left-justified, I2S, and right-justified
(16-, 18-, 20-, 24-bit) modes. Additionally, the serial output
port supports TDM Mode for daisy-chaining multiple AD1895s to
a digital signal processor. The serial output data is dithered down
to 20, 18, or 16 bits when 20-, 18-, or 16-bit output data is
selected. The AD1895 sample rate converts the data from the
serial input port to the sample rate of the serial output port. The
sample rate at the serial input port can be asynchronous with
respect to the output sample rate of the output serial port. The
master clock to the AD1895, MCLK, can be asynchronous to
both the serial input and output ports.
MCLK can either be generated off-chip or on-chip by the AD1895
master clock oscillator. Since MCLK can be asynchronous to the
input or output serial ports, a crystal can be used to generate
MCLK internally to reduce noise and EMI emissions on the
board. When MCLK is synchronous to either the output or input
serial port, the AD1895 can be configured in a master mode where
MCLK is divided down and used to generate the left/right
and bit clocks for the serial port that is synchronous to MCLK.
The AD1895 supports master modes of 256 × fS, 512 × fS, and
768 × fS for both input and output serial ports.
Conceptually, the AD1895 interpolates the serial input data by
a rate of 220 and samples the interpolated data stream by the
output sample rate. In practice, a 64-tap FIR filter with 220
polyphases, a FIFO, a digital servo loop that measures the time
difference between input and output samples within 5 ps, and a
digital circuit to track the sample rate ratio are used to perform
the interpolation and output sampling. Refer to the Theory of
Operation section. The digital servo loop and sample rate ratio
circuit automatically track the input and output sample rates.
(continued on page 15)
FEATURES
Automatically Senses Sample Frequencies
No Programming Required
Attenuates Sample Clock Jitter
3.3 V to 5 V Input and 3.3 V Core Supply Voltages
Accepts 16-/18-/20-/24-Bit Data
Up to 192 kHz Sample Rate
Input/Output Sample Ratios from 7.75:1 to 1:8
Bypass Mode
Multiple AD1895 TDM Daisy-Chain Mode
128 dB Signal-to-Noise and Dynamic Range
(A-Weighted, 20 Hz to 20 kHz BW)
Up to –122 dB THD + N
Linear Phase FIR Filter
Hardware Controllable Soft Mute
Supports 256 � fS, 512 � fS, or 768 � fS Master Mode
Clock
Flexible 3-Wire Serial Data Port with Left-Justified,2S, Right-Justified (16-, 18-, 20-, 24-Bit), and TDM
Serial Port Modes
Master/Slave Input and Output Modes
28-Lead SSOP Plastic Package
APPLICATIONS
Home Theater Systems, Automotive Audio Systems,
DVD, DVD-R, CD-R, Set-Top Boxes, Digital Audio
Effects Processors*Patents pending.
AD1895–SPECIFICATIONS
TEST CONDITIONS, UNLESS OTHERWISE NOTED.Supply Voltages
VDD_CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 V
VDD_IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 V or 3.3 V
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25°C
Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.0 MHz
Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . 1.000 kHz, 0 dBFS
Measurement Bandwidth . . . . . . . . . . . . . . . . . . 20 to fS_OUT/2 Hz
Word Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Bits
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 pF
Input Voltage High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 V
Input Voltage Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 V
DIGITAL PERFORMANCE (VDD_CORE = 3.3 V � 5%, VDD_IO = 5.0 V � 10%)SAMPLE RATE RATIOS
DYNAMIC RANGE
NOTESLower sampling rates than those given by this formula are possible, but the jitter rejection will decrease.Refer to the Typical Performance Characteristics section for DNR and THD + N numbers over a wide range of input and output sample rates.For any other ratio, minimum THD + N will be better than –115 dB. Please refer to detailed performance plots.
AD1895
DIGITAL TIMING (–40�C < TA < +105�C, VDD_CORE = 3.3 V � 5%, VDD_IO = 5.0 V � 10%)NOTESRefer to Timing Diagrams section.The maximum possible sample rate is: FSMAX = fMCLK/138.fMCLK of up to 34 MHz is possible under the following conditions: 0°C < TA < 70°C, 45/55 or better MCLK_IN duty cycle.
Specifications subject to change without notice.
TIMING DIAGRAMSFigure 2.RESET Timing
Figure 3.MCLK_IN Timing
AD1895
DIGITAL FILTERS (VDD_CORE = 3.3 V � 5%, VDD_IO = 5.0 V � 10%)Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Specifications subject to change without notice.
DIGITAL I/O CHARACTERISTICS (VDD_CORE = 3.3 V � 5%, VDD_IO = 5.0 V � 10%)Input Voltage Low (VIL)
Specifications subject to change without notice.
POWER SUPPLIESACTIVE SUPPLY CURRENT
*For 3.3 V tolerant inputs, VDD_IO supply should be set to 3.3 V; however, VDD_CORE supply voltage should not exceed VDD_IO.
Specifications subject to change without notice.
–SPECIFICATIONS
AD1895
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1895 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
POWER SUPPLIES (VDD_CORE = 3.3 V � 5%, VDD_IO = 5.0 V � 10%)Specifications subject to change without notice.
TEMPERATURE RANGESpecifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS**Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
ORDERING GUIDE
