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AD1893JST ,Low Cost SamplePort 16-Bit Stereo Asynchronous Sample Rate ConverterSPECIFICATIONSTEST CONDITIONS UNLESS OTHERWISE NOTEDSupply Voltage +3.0 VAmbient Temperature 25

AD1893JST
Low Cost SamplePort 16-Bit Stereo Asynchronous Sample Rate Converter
SYSTEM DIAGRAM
INPUT SERIAL DATAOUTPUT SERIAL DATA
INPUT SAMPLE CLOCK
REV.A
FEATURES
Low Cost
LQFP and PDIP Packages
3 V Supply Performance Specified—Very Low Power
Automatically Senses Sample Frequencies—No
Programming Required
Rejects Sample Clock Jitter
Accommodates Dynamically Changing Asynchronous
Sample Clocks
8 kHz to 56 kHz Sample Clock Frequency Range
Approximately 1:2 to 2:1 Ratio Between Sample
Clocks
–96 dB THD+N at 1 kHz
96 dB Dynamic Range
Optimal Clock Tracking Control—Slow/Fast Settling
Modes
Linear Phase in All Modes
Automatic Output Mute
Flexible Four-Wire Serial Interfaces with Right-Justified
Mode
Power-Down Mode
On-Chip Oscillator
APPLICATIONS
Consumer CD-R, DAT, DCC, MD and 8 mm Video Tape
Recorders Including Portables
Digital Audio Communication/Network Systems
Computer Multimedia Systems
PRODUCT OVERVIEW
The AD1893 SamplePort is a fully digital, stereo Asynchronous
Sample Rate Converter (ASRC) that solves sample rate interfacing
and compatibility problems in digital audio equipment. Concep-
tually, this converter interpolates the input data up to a very high
internal sample rate with a time resolution of 300ps, then deci-
mates down to the desired output sample rate. The AD1893 is
intended for 16-bit low cost, non-varispeed applications where low
voltage, low power (i.e., battery-powered) operation is required.
Refer to the AD1890/AD1891 data sheet for other products in the
SamplePort family. This device is asynchronous because the fre-
quency and phase relationships between the input and output
sample clocks (both are inputs to the AD1893 ASRC) are arbitrary
and need not be related by a simple integer ratio. There is no need
to explicitly select or program the input and output sample clock
frequencies, as the AD1893 automatically senses the relationship
between the two clocks. The input and output sample clock fre-
quencies can nominally range from 8 kHz to 56 kHz, and the ratio
between them can vary from approximately 1:2 to 2:1.
SamplePort is a registered trademark of Analog Devices, Inc.
Low Cost SamplePort®
16-Bit Stereo Asynchronous
Sample Rate Converter
The AD1893 uses multirate digital signal processing techniques
to construct an output sample stream from the input sample
stream. The input word width is 4 to 16 bits for the AD1893.
Shorter input words are automatically zero-filled in the LSBs.
The output word width is 24 bits. The user can receive as many
of the output bits as desired. Internal arithmetic is performed
with 22-bit coefficients and 27-bit accumulation. The digital
samples are processed with unity gain.
The input and output control signals allow for considerable
flexibility for interfacing to a variety of DSP chips, AES/EBU
receivers and transmitters and for I2S compatible devices. Input
and output data can be independently right- or left- (with or
without a one bit clock delay) justified to the left/right clock
edge. In the right-justified mode, the MSB is delayed 16-bit
clock periods from the left/right clock edge transition. Input and
output data can also be independently justified to the word
clock rising edge. The data justification options are encoded on
two mode pins for both the input port and the output port. The
bit clocks can also be independently configured for rising edge
active or falling edge active operation.
The AD1893 SamplePort ASRC has on-chip digital coefficients
that correspond to a highly oversampled 0 Hz to 20 kHz low-
pass filter with a flat passband, a very narrow transition band,
and a high degree of stopband attenuation. A subset of these
filter coefficients are dynamically chosen on the basis of the
filtered ratio between the input sample clock (LR_I) and the
output sample clock (LR_O), and these coefficients are then
used in an FIR convolver to perform the sample rate conversion.
Refer to the Theory of Operation section of this data sheet for a
more thorough functional description. The low-pass filter has
been designed so that full 20 kHz bandwidth is maintained
when the input and output sample clock frequencies are as low
as 44.1 kHz. If the output sample rate drops below the input
sample rate, the bandwidth of the input signal is automatically
(continued on Page 4)
AD1893–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltage+3.0V
Ambient Temperature25°C
Crystal Frequency16MHz
Load Capacitance100pF
All minimums and maximums tested except as noted.
PERFORMANCE1 (Guaranteed for VDD = +3.3 V to +5.0 V – 10%)
DIGITAL INPUTS (Guaranteed for VDD = +3.0 V to +5.0 V – 10%)
DIGITAL TIMING (Guaranteed for VDD = +3.0 V to +5.0 V – 10%) See Figures 26 through 28.
AD1893
DIGITAL FILTER CHARACTERISTICS1
POWER (FSIN = 48 kHz, FSOUT = 44.1 kHz)
TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS3
NOTESGuaranteed, Not TestedValid only when FSOUT ‡ FSIN (i.e., upsampling), FSIN = 44.1 kHz.Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of
the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Specifications subject to change without notice.
ORDERING GUIDE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1893 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
AD1893
(continued from Page 1)
PRODUCT OVERVIEW (Continued)
limited to avoid alias distortion on the output signal. The
AD1893 dynamically alters the low-pass filter cutoff frequency
smoothly and slowly, so that real-time variations in the sample
rate ratio are possible without degradation of the audio quality.
The AD1893 has a pin selectable slow- or fast-settling mode.
This mode determines how quickly the ASRC adapts to a
change in either the input sample clock frequency (FSIN) or the
output sample clock frequency (FSOUT). In the slow-settling
mode, the control loop which computes the ratio between FSIN
and FSOUT settles in approximately 800 ms and begins to reject
jitter above 3 Hz. The slow-settling mode offers the best signal
quality and the greatest jitter rejection. In the fast-settling mode,
the control loop settles in approximately 200 ms and begins to
reject jitter above 12 Hz. The fast-settling mode allows rapid,
real time sample rate changes to be tracked without error, at the
expense of some narrowband noise modulation products on the
output signal.
The AD1893 features short group delay processing. This feature
relates to the depth of the First-In, First-Out (FIFO) memory,
which buffers the input data samples before they are processed
by the FIR convolver. In the AD1893, the group delay is
approximately 700ms. If the read and write pointers that
manage the FIFO cross (indicating underflow or overflow), the
AD1893 asserts the mute output (MUTE_O) pin HI for 128
output clock cycles. If MUTE_O is connected to the mute input
(MUTE_I) pin, as it normally should be, the serial output will
be muted (i.e., all bits zero) during this transient event.
The AD1893 includes an on-chip oscillator that only requires
the user provide an external crystal. By removing the need for
an external oscillator, the AD1893 lowers the total cost of own-
ership to the end user. The AD1893 also includes a power-
down mode, which is invoked with the PWRDWN pin.
Asserting this control signal HI will place the AD1893 into a
very low power dissipation in active and standby condition.
The AD1893 is fabricated in a 0.8 mm single poly, double metal
CMOS process and are packaged in a 0.6" wide 28-lead plastic
DIP and a 10 mm by 10 mm body size 44-lead LQFP. The
AD1893 operates from a +3 V to +5 V power supply over the
temperature range of 0°C to +70°C.
DEFINITIONS
Dynamic Range
The ratio of a near full-scale input signal to the integrated noise
in the passband (0 kHz to »20 kHz), expressed in decibels (dB).
Dynamic range is measured with a –60 dB input signal and
“60 dB” arithmetically added to the result.
Total Harmonic Distortion + Noise
Total Harmonic Distortion plus Noise (THD+N) is defined as
the ratio of the square root of the sum of the squares of the values
of the harmonics and noise to the rms value of a sinusoidal
input signal. It is usually expressed in percent (%) or decibels.
Interchannel Phase Deviation
Difference in input sampling times between stereo channels,
expressed as a phase difference in degrees between 1 kHz inputs.
Group Delay
Intuitively, the time interval required for a full-level input pulse
to appear at the converter’s output, at full level, expressed in
milliseconds (ms). More precisely, the derivative of radian
phase with respect to radian frequency at a given frequency.
Transport Delay
The time interval between when an impulse is applied to the
converter’s input and when the output starts to be affected by
this impulse, expressed in milliseconds (ms). Transport delay is
independent of frequency.
AD1893 PIN LIST
Serial Input Interface
Serial Output Interface
Input Control Signals
PIN CONFIGURATIONS
DIP
XTAL_I
DATA_I
BCLK_I
WCLK_I
VDD
GND
BKPOL_I
MODE0_I
MODE1_I
GND
RESET
LR_I
SETSLW
PWRDWN
BCLK_O
WCLK_O
DATA_O
VDD
GND
BKPOL_O
MODE0_O
MODE1_O
MUTE_O
MUTE_I
LR_O
NC = NO CONNECT
XTAL_O
LQFP
NC = NO CONNECT
WCLK_O
VDD
GND
DATA_O
BCLK_I
VDD
GND
WCLK_IDATA_IXTAL_ONCSETSLWXTAL_I
MODE1_I
GND
MUTE_IPWRDWNBCLK_ONC
MUTE_O
MODE1_ONC
BKPOL_O
MODE0_O
BKPOL_I
MODE0_I
LR_I
LR_O
RESET
AD1893
Output Control Signals
Miscellaneous
PWRDWN
Power Supply Connections
THEORY OF OPERATION
There are at least two logically equivalent methods of explaining
the concept of asynchronous sample rate conversion: the high
speed interpolation/decimation model and the polyphase filter
bank model. Using the AD1893 SamplePort does not require
understanding either model. This section is included for those
who wish a deeper understanding of its operation.
Interpolation/Decimation Model
In the high speed interpolation/decimation model, illustrated in
Figure 1, the sampled data input signal (Plot A in Figure 1) is
interpolated at some ratio (IRATIO) by inserting IRATIO-1
zero valued samples between each of the original input signal
samples (Plot B in Figure 1). The frequency domain charac-
teristics of the input signal are unaltered by this operation, ex-
cept that the zero-padded sequence is considered to be sampled
at a frequency which is the product of original sampling fre-
quency multiplied by IRATIO.
The zero-padded values are fed into a digital FIR low-pass filter
(Plot C in Figure 1) to smooth or integrate the sequence, and
limit the bandwidth of the filter output to 20 kHz. The inter-
polated output signal has been quantized to a much finer time
scale than the original sequence. The interpolated sequence is
INPUT
SIGNAL
OUTPUT
SIGNALDE
TIME
AMP
Figure 1.Interpolation/Decimation Model—Time Domain View
then passed to a zero-order hold functional block (physically
implemented as a register, Plot D in Figure 1) and then asyn-
chronously resampled at the output sample frequency (Plot E in
Figure 1). This resampling can be thought of as a decimation
operation since only a very few samples out of the great many
interpolated samples are retained. The output values represent
the “nearest” values, in a temporal sense, produced by the inter-
polation operation. There is always some error in the output
sample amplitude due to the fact that the output sampling switch
does not close at a time that exactly corresponds to a point on the
fine time scale of the interpolated sequence. However, this error
can be made arbitrarily small by using a very large interpolation
ratio. The AD1893 SamplePort ASRC uses an equivalent IRATIO
of 65,536 to provide 16-bit accuracy (»–96dB THD+N) across
the 0 kHz to 20 kHz audio band.
The number of FIR filter taps and associated coefficients is
approximately 4 million. The equivalent FIR filter convolution
frequency (or “upsample” frequency) is 3.2768 GHz, and the
fine time scale has resolution of about 300 ps. Various propri-
etary efficiencies are exploited in the AD1893 ASRC to reduce
the complexity and throughput requirements of the hardware
implied by this interpolation/decimation model.
AD1893
Polyphase Filter Bank Model
Although less intuitively understandable than the interpolation/
decimation model, the polyphase filter bank model is useful to
explore because it more accurately portrays the operation of the
actual AD1893 SamplePort hardware. In the polyphase filter
bank model, the stored FIR filter coefficients are thought of as
the impulse response of a highly oversampled 0 kHz to 20 kHz
low-pass prototype filter, as shown in Figure 2. If this low-pass
filter is oversampled by a factor of N, then it can be conceptu-
ally decomposed into N different “subfilters,” each filter consist-
ing of a different subset of the original set of impulse response
samples. If the temporal position of each of the subfilters is
maintained, then they can be summed to recreate the original
oversampled impulse response. Since the original impulse re-
sponse is highly oversampled, the more sparsely sampled
subfilters still individually meet the Nyquist criterion (i.e., they
AMP
TIME
OVERSAMPLED
PHASE
0 Deg
1/4FS1/2FS3/4FSFS
FREQ
AMP
1/4FS1/2FS3/4FSFS
1/4FS1/2FS3/4FSFS
1/4FS1/2FS3/4FSFS
1/4FS1/2FS3/4FSFS
Figure 2.Four Polyphase Subfilters in the Time and Frequency Domains
are adequately sampled). The baseband magnitude and phase
responses of the subfilters are identical. The out-of-band (i.e.,
alias) regions of the subfilters however have phase responses
which are shifted relative to one another, in a manner that
causes them to cancel when they are summed.
The subfilter coefficients are then aligned to the left, as shown
in Figure 3, so that the first coefficient of each subfilter is
aligned to the first point on a coarse time scale. (This conceptual
step accounts for how the hardware implementation is able to
operate at the slower rate corresponding to the coarse time
scale.) Each subfilter has been shifted in time by a different
amount, and though they still share identical magnitude re-
sponses, they now have in-band phase responses which have
fractionally different slopes (i.e., group delays).
AMP
TIME
SUBFILTER COEFFICIENTS
ALIGNED TO THE LEFT
TSIN = 1/FSIN
FREQ
FSIN/2
FSIN/2
FSIN/2
FSIN/2
FSIN/2
PHASE
DELAY = NOMINAL
DELAY = NOMINAL
DELAY = NOMINAL – .25/FSIN
DELAY = NOMINAL – .5/FSIN
DELAY = NOMINAL – .75/FSIN
Figure 3.Four Polyphase Subfilters Realigned to Coarse Time GridINPUT
SIGNALOUTPUT
SIGNAL
Figure 4.Polyphase Filter Bank Model—Conceptual Block
Diagram
The full set of subfilters can be considered to form a parallel
bank of “polyphase” filters which have decrementing, linear
phase group delays. All of the polyphase filters conceptually
process the input signal simultaneously, as illustrated in Figure
4, at the input sample rate.
Asynchronous sample rate conversion under the polyphase filter
bank model is accomplished by selecting the output of a particu-
lar polyphase filter on the basis of the temporal relationship
between the input sample clock and the output sample clock
events. Figure 5 shows the desired filter group delay as a func-
tion of the relative time difference between the current output
sample clock and the last input sample clock. If an output
sample is requested late in the input sample period, then a short
filter delay is required, and if an output sample is requested
early in the input sample period, then a long filter delay is re-
quired. This nonintuitive result arises from the fact that FIR
filters always produce some delay, so that selecting a filter with
shorter delay moves the interpolated sample closer to the newest
input sample.
AD1893
OUTPUT SEQUENCEPASTFUTURE
AMPLITUDE
AMPLITUDE
SHORT
DELAY
LONG
DELAY
SMALL
OFFSET
LARGE
OFFSET
Figure 5.Input and Output Clock Event Relationship
A short delay corresponds to a large offset into the dense FIR
filter coefficient array, and a long delay corresponds to a small
offset. Note that because the output sample clock can arrive at
any arbitrary time with respect to the input sample clock, the
selection of a polyphase filter with which to convolve the input
sequence occurs on every output sample clock event. Occasion-
ally the FIFO which holds the input sequence in the FIR con-
volver is either not incremented, or incremented by two between
output sample clocks (see periods A and B in Figure 5); this
happens more often when the input and output sample clock
frequencies are dissimilar than when they are close together.
However, in this situation, an appropriate polyphase filter is
selected to process the input signal, and thus an accurate output
sample is computed. Input and output samples are not skipped
or repeated (unless the input FIFO underflows or overflows), as
is the case in some other sample rate converter implementations.
To obtain an accurate conversion, a large number of polyphase
filters are needed. The AD1893 SamplePort uses the equivalent
of 65,536 polyphase filters to achieve its high quality distortion
and dynamic range specifications.
Sample Clock Tracking
It should be clear that, in either model, the correct computation
of the ratio between the input sample rate (as determined from
the left/right input clock, LR_I) and the output sample rate (as
determined from the left/right output clock, LR_O) is critical to
the quality of the output data stream. It is straightforward to
compute this ratio if the sample rates are fixed and synchronous;
the challenge is to accurately track dynamically varying and
asynchronous sample rates, as well as to account for jitter.
The AD1893 SamplePort solves this problem by embedding the
ratio computation circuit within a digital servo control loop, as
shown in Figure 6. This control loop includes special provisions
to allow for the accurate tracking of dynamically changing
sample rates. The outputs of the control loop are the starting
read addresses for the input data FIFO and the filter coefficient
ROM. These start addresses are used by the FIFO and ROM
address generators, as shown in Figure 6.
The input data FIFO write address is generated by a counter
which is clocked by the input sample clock (i.e., LR_I). It is very
important that the FIFO read address and the FIFO write ad-
dress do not cross, as this means that the FIFO has either
underflowed or overflowed. This consideration affects the
choice of settling time of the control loop. When a step change
in the sample rate occurs, the relative positions of the read and
write addresses will change while the loop is settling. A fast
settling loop will act to keep the FIFO read and write addresses
separated better than a slow settling loop. The AD1893 includes
a user selectable pin (SETLSLW) to set the loop settling time
that essentially changes the coefficients of the digital servo con-
trol loop filter. The state of the SETLSLW pin can be changed
on-the-fly but is normally set and forgotten.
Figure 6.Functional Block Diagram

Partno	Mfg	Dc	Qty	Available	Descript
AD1893JST		N/a	6	avai	Low Cost SamplePort 16-Bit Stereo Asynchronous Sample Rate Converter