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AD1892JR ,Integrated Digital Receiver/Rate ConverterSPECIFICATIONSTEST CONDITIONS UNLESS OTHERWISE NOTEDSupply Voltage +5.0 VAmbient Temperature 25

AD1892JR
Integrated Digital Receiver/Rate Converter
REV.0
FEATURES
Complete EIAJ CP-340 (CP-1201), IEC-958, AES/EBU,
S/PDIF Compatible Digital Audio Receiver and
Asynchronous Sample Rate Converter
Status Pins and Microprocessor Interfaces for
Stand-Alone and Microcontroller-Oriented Operation
Integrated Channel Status Buffer and Q-Channel
Subcode Buffer (Supports EIAJ CP-2401)
20-Bit SamplePort® Architecture Provides Superb Jitter
Rejection on Input Port
Sample Rate Conversion from 8 kHz to 48 kHz with
1:5 Upsampling Range
1:0.85 Downsampling Range
120 dB Dynamic Range
–113 dB THD+N @ 1 kHz
CRC Calculation on Q-Channel Subcode (Consumer
Mode Only) and on Channel Status (Pro Mode Only)
Four-Wire SPI™ Compatible Serial Control Port
Mute Input Pin
Power-Down Mode
Single +5 V Supply
Flexible Three-Wire Serial Data Port with Left-Justified,
Right-Justified and I2S-Compatible Modes
28-Lead SOIC Package
APPLICATIONS
DVD, DAT, MD, DCC and CD-R Recorders and Players
Computer Multimedia Products
DAB Receivers, Automotive Digital Audio Networks
Integrated Digital
Receiver/Rate Converter
PRODUCT OVERVIEW
The AD1892 combines a CP-1201, CP-340, IEC-958, AES/
EBU, S/PDIF compatible Digital Audio Receiver (DAR) with
an asynchronous sample rate converter, allowing the user to
specify the output sample rate of the received digital audio infor-
mation. The DAR block features support for both Q-channel
subcode information (to support CD, CD-R, MD and DAT
digital audio formats) as well as Channel Status information. A
microcontroller interface, with an SPI compatible serial port,
allows full access to the 80-bit Q-Channel subcode buffer and to
the 32-bit Channel Status buffer, as well as to the control and
status registers. Additionally, key status information from the
incoming subframes and the Channel Status buffer is reported
on status output pins on the AD1892, so the AD1892 may be
used in systems that do not include a microcontroller or
microprocessor.
The asynchronous sample rate converter block is based on
market leading AD1890 family SamplePort rate conversion tech-
nology. The AD1892 offers a 1:5 upsampling range, and will
downsample from 48 kHz to 44.1 kHz. Input audio word widths
up to 20 bits are supported, and output audio word widths of 16
or 20 are supported, with 120 dB of dynamic range and –113dB
THD+N. The rate converter inherently rejects jitter on the
recovered clocks from the incoming biphase-mark encoded
stream. Indeed, sample rate conversion is highly synergistic
with digital audio reception, allowing the use of a fully digital
phase locked loop clock recovery scheme with highly robust
clock recovery and jitter rejection.
(continued on Page 4)
FUNCTIONAL BLOCK DIAGRAM
SamplePort is a registered trademark of Analog Devices, Inc.
SPI is a trademark of Motorola, Inc.
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltage+5.0V
Ambient Temperature25°C
Output Sample Frequency (FSOUT)48.8kHz
MCLK25MHz (512 · FSOUT)
Input Word Width20Bits
Load Capacitance100pF
All minimums and maximums tested except as noted.
PERFORMANCE1
DIGITAL I/O1
DIGITAL TIMING1
DIGITAL RS-422 RECEIVERS (RXP, RXN Pins Only)
AD1892–SPECIFICATIONS
POWER
TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS2
DIGITAL FILTER CHARACTERISTICS1
NOTESGuaranteed, not tested.Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of
the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Specifications subject to change without notice.
ORDERING GUIDE
AD1892
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1892 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD1892
AD1892 PIN LIST
Biphase-Mark Serial Input
Serial Output Interface
Decoded Channel Status Outputs
(continued from Page 1)
PRODUCT OVERVIEW (Continued)
In addition to the Q-channel subcode and Channel Status buff-
ers, the AD1892 includes two 8-bit control registers and two 8-
bit status registers. The output data interface may be configured
in left-justified, I2S-justified and right-justified modes. The
AD1892 includes hardware power-down/reset and mute control
inputs, and power-down/reset and mute may also be invoked
through write to bits in the control registers. The AD1892
operates from a master clock that must be synchronous with the
output sample rate at 512 · FS. Cyclic Redundancy Coding
(CRC) error detection is performed over the full 80 bits of the
received Q-channel subcode information in consumer mode, as
well as the full 192 bits of the received Channel Status informa-
tion in professional mode.
The AD1892 includes a SYNC input (Pin 23) that allows
multiple AD1892s in a system to be synchronized to a common
LEFT/RIGHT clock.
The AD1892 is offered in a 28-lead SOIC package. It operates
over the industrial temperature range from –40°C to +85°C
at a supply voltage from 4.5 V to 5.5 V. The only external
components required to support the AD1892 are power supply
decoupling capacitors.
DEFINITIONS
Dynamic Range
The ratio of a full-scale input signal to the integrated noise in the
passband (0 kHz to »20 kHz), expressed in decibels (dB).
Dynamic range is measured with a –60 dB input signal and
“60 dB” arithmetically added to the result. This measurement
technique is consistent with the recommendations of the Audio
Engineering Society (AES17-1991) and the Electronic Industries
Association of Japan (EIAJ CP-307).
Total Harmonic Distortion + Noise
Total Harmonic Distortion plus Noise (THD+N) is defined as
the ratio of the square root of the sum of the squares of the
values of the harmonics and noise to the value of the fundamen-
tal input frequency. It is usually expressed in percent (%) or
decibels.
Interchannel Phase Deviation
Difference in input sampling times between stereo channels,
expressed as a phase difference in degrees between 1 kHz inputs.
Group Delay
The time interval required for the frequency components of an
input pulse to appear at the converter’s output, expressed in
milliseconds (ms). More precisely, the derivative of radian phase
with respect to radian frequency at a given frequency.
Decoded Channel Status Outputs (Continued)
CON/PRO
AD1892
Subframe Status Outputs
INT
U/CBIT
SFCLK
Q-Channel Subcode Clock Output Signal
Serial Control Port Signals
SDO
Power Supply Connections
Miscellaneous
PIN CONFIGURATION
PD/RST
LRCLK
BCLK
MUTE
MCLK
CCLK
SDI
DVDD
SYNC
SDATASDO
QDFS
DGND
SFCLK
U/CBIT
INTCC
ERROR
NOSIG
RXP
RXN
CON/PRO
CSCLK
AD1892
SERIAL DIGITAL AUDIO TRANSMISSION STANDARDS
The AD1892 can receive S/PDIF (Sony/Philips Digital Interface
Format), AES/EBU (Audio Engineering Society/European
Broadcasting Union, also known as AES3-1992), IEC-958
(International Electrotechnical Commission) and CP-340 (EIAJ
[Electronic Industry Association of Japan] CP-1201) serial
streams. S/PDIF is a consumer audio standard, and AES/EBU
is a professional audio standard; IEC-958 and CP-340 have
both consumer and professional definitions. This data sheet is
not intended to fully define or to provide a tutorial for these
standards; please contact these international standards setting
bodies for the full specifications.
All of these digital audio serial communication schemes encode
audio data and audio control information using the biphase-
mark method. This encoding method minimizes the dc content
of the transmitted signal and allows the receiver to decode clock
information from the transmitted signal. As can be seen from
Figure 1, ones in the original data end up with midcell transi-
tions in the biphase-mark encoded data, while zeros in the origi-
nal data do not. Note that the biphase-mark encoded data
always has a transition between bit boundaries.
BIPHASE-MARK
DATA
DATA
CLOCK
(2 TIMES BIT RATE)
Figure 1.Biphase-Mark Encoding
Digital audio communication schemes use “preambles” to dis-
tinguish between channels (called “subframes”) and between
longer term control information blocks (called “frames”). Pre-
ambles are particular biphase-mark patterns, which contain
encoding violations that allow the receiver to uniquely recognize
them. These patterns, and their relationship to frames and
subframes, are shown in Figures 2 and 3.
Figure 2.Biphase-Mark Encoded Preambles
Figure 3.Preambles, Frames and Subframes
The biphase-mark encoding violations are shown in Figure 4.
Note that all three preambles include encoding violations. Or-
dinarily, the biphase-mark encoding method results in a polarity
transition between bit boundaries.
Figure 4.Preambles
As noted above, these serial digital audio communication
schemes are organized using a frame and subframe construction.
There are two subframes per frame (ordinarily the left and right
channel). Each subframe includes the appropriate four bit
preamble, four bits of “auxiliary” (aux) data, 20 bits of audio
data (LSB first), a “validity” (V) bit, a “user” (U) data bit, a
Channel Status (C) bit and an even parity (P) bit. The Channel
Status bits and the user bits accumulate over many frames to
convey control information. The Channel Status bits accumu-
late over a 192 frame period (called a Channel Status block).
The user bits accumulate over 1176 frames when the inter-
connect is implementing the so-called “subcode” scheme
(EIAJ CP-2401). The organization of the Channel Status
block, frames and subframes is shown in Figure 5.
As noted above, the Channel Status bit from each subframe
accumulates over a 192 subframe period. The standards allow for
the Channel Status bit in each subframe to be independent, but
ordinarily the Channel Status bit in the two subframes of each
frame are the same. The Channel Status bits are defined
VALIDITY
USER DATA
CHANNEL STATUS DATA
EVEN PARITY BIT
A = LEFT CHANNEL
192 LEFT, 192 RIGHT
Figure 5.Block, Frame and Subframe Organization
differently for the consumer audio standards and the profes-
sional audio standards. The 192 Channel Status bits are
organized into 24 bytes and have the interpretations shown in
Figures 6 through 16.
AD1892
Figure 8.Consumer Channel Status Byte 0
Figure 9.Consumer Channel Status Byte 1
Figure 10.Consumer Channel Status Byte 2
Figure 11.Consumer Channel Status Bytes 3 Through 23
Figure 12.Professional Channel Status Bytes 0 and 1
AD1892
Figure 13.Professional Channel Status Byte 2
Figure 14.Professional Channel Status Bytes 3 Through 5
Figure 15.Professional Channel Status Bytes 6
Through 21
Figure 16.Professional Channel Status Bytes 22 and 23

Partno	Mfg	Dc	Qty	Available	Descript
AD1892JR	ADI	N/a	45	avai	Integrated Digital Receiver/Rate Converter