AD1890JN ,SamplePort Stereo Asynchronous Sample Rate Convertersapplicationsthe filtered instantaneous ratio between the input sample clockwhere large dynamic samp ..
AD1890JP ,SamplePort Stereo Asynchronous Sample Rate ConvertersSPECIFICATIONSTEST CONDITIONS UNLESS OTHERWISE NOTEDSupply Voltage +5.0 VAmbient Temperature 25 °CM ..
AD1891JN ,SamplePort Stereo Asynchronous Sample Rate ConvertersFEATURESAutomatically Sense Sample Frequencies—NoProgramming RequiredEXAMPLE EXAMPLETolerant of Sam ..
AD1892JR ,Integrated Digital Receiver/Rate ConverterSPECIFICATIONSTEST CONDITIONS UNLESS OTHERWISE NOTEDSupply Voltage +5.0 VAmbient Temperature 25
AD1890JN-AD1890JP-AD1891JN
SamplePort Stereo Asynchronous Sample Rate Converters
SYSTEM DIAGRAMREV.0
SamplePort Stereo Asynchronous
Sample Rate Converters
FEATURES
Automatically Sense Sample Frequencies—No
Programming Required
Tolerant of Sample Clock Jitter
Smooth Transition When Sample Clock Frequencies
Cross
Accommodate Dynamically Changing Asynchronous
Sample Clocks
8 kHz to 56 kHz Sample Clock Frequency Range
1:2 to 2:1 Ratio Between Sample Clocks
–106 dB THD+N at 1 kHz (AD1890)
120 dB Dynamic Range (AD1890)
Optimal Clock Tracking Control
–Short/Long Group Delay Modes
–Slow/Fast Settling Modes
Linear Phase in All Modes
Equivalent of 4 Million 22-Bit FIR Filter Coefficients
Stored On-Chip
Automatic Output Mute
Flexible Four Wire Serial Interfaces
Low Power
APPLICATIONS
Digital Mixing Consoles and Digital Audio Workstations
CD-R, DAT, DCC and MD Recorders
Multitrack Digital Audio and Video Tape Recorders
Studio to Transmitter Links
Digital Audio Signal Routers/Switches
Digital Audio Broadcast Equipment
High Quality D/A Converters
Digital Tape Recorder Varispeed Applications
Computer Communication and Multimedia Systems
PRODUCT OVERVIEWThe AD1890 and AD1891 SamplePorts™ are fully digital, stereo
Asynchronous Sample Rate Converters (ASRCs) that solve sample
rate interfacing and compatibility problems in digital audio equip-
ment. Conceptually, these converters interpolate the input data up
to a very high internal sample rate with a time resolution of 300 ps,
then decimate down to the desired output sample rate. The
AD1890 is intended for 18- and 20-bit professional applications,
and the AD1891 is intended for 16-bit lower cost applications
where large dynamic sample-rate changes are not encountered.
These devices are asynchronous because the frequency and phase
relationships between the input and output sample clocks (both are
inputs to the AD1890/AD1891 ASRCs) are arbitrary and need not
be related by a simple integer ratio. There is no need to explicitly
select or program the input and output sample clock frequencies, as
the AD1890/AD1891 automatically sense the relationship between
SamplePort and SamplePorts are trademarks of Analog Devices, Inc.
the two clocks. The input and output sample clock frequencies
can nominally range from 8 kHz to 56 kHz, and the ratio
between them can vary from 1:2 to 2:1.
The AD1890/AD1891 use multirate digital signal processing
techniques to construct an output sample stream from the input
sample stream. The input word width is 4 to 20 bits for the
AD1890 or 4 to 16 bits for the AD1891. Shorter input words
are automatically zero-filled in the LSBs. The output word
width for both devices is 24 bits. The user can receive as many
of the output bits as desired. Internal arithmetic is performed
with 22-bit coefficients and 27-bit accumulation. The digital
samples are processed with unity gain.
The input and output control signals allow for considerable flex-
ibility for interfacing to a variety of DSP chips, AES/EBU
receivers and transmitters and for I
and output data can be independently justified to the left/right
clock edge, or delayed by one bit clock from the left/right clock
edge. Input and output data can also be independently justified
to the word clock rising edge or delayed by one bit clock from
the word clock rising edge. The bit clocks can also be indepen-
dently configured for rising edge active or falling edge active
operation.
The AD1890/AD1891 SamplePort™ ASRCs have on-chip digi-
tal coefficients that correspond to a highly oversampled 0 kHz to
20 kHz low-pass filter with a flat passband, a very narrow tran-
sition band, and a high degree of stopband attenuation. A subset
of these filter coefficients are dynamically chosen on the basis of
the filtered instantaneous ratio between the input sample clock
(LR_I) and the output sample clock (LR_O), and these coeffi-
cients are used in an FIR convolver to perform the sample rate
conversion. Refer to the “Theory of Operation” section of this
data sheet for a more thorough functional description. The low-
pass filter has been designed so that full 20 kHz bandwidth is
maintained when the input and output sample clock frequencies
are as low as 44.1 kHz. If the output sample rate drops below
the input sample rate, the bandwidth of the input signal is
AD1890/AD1891–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTEDAll minimums and maximums tested except as noted.
PERFORMANCE (Guaranteed over 0°C ≤ TA ≤ 70°C, VDD = 5.0 V ± 10%, 8 MHz ≤ MCLK ≤ 20 MHz)
DIGITAL INPUTS (Guaranteed over 0°C ≤ TA ≤ 70°C, VDD = 5.0 V ± 10%, 8 MHz ≤ MCLK ≤ 20 MHz)
DIGITAL TIMING (Guaranteed over 0°C ≤ TA ≤ 70°C, VDD = 5.0 V ± 10%, 8 MHz ≤ MCLK ≤ 20 MHz)
POWER (0°C ≤ TA ≤ 70°C, MCLK = 16 MHz, FSIN = 48 kHz, FSOUT = 44.1 kHz)
TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS**Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
DIGITAL FILTER CHARACTERISTICS††Guaranteed. Not TestedValid only when FSOUT ≥ FSIN (i.e., upsampling), FSIN = 44.1 kHz.
Specifications subject to change without notice.
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1890/AD1891 features proprietary ESD protection circuitry, permanent
AD1890/AD1891(continued from Page 1)
PRODUCT OVERVIEW (Continued)automatically limited to avoid alias distortion on the output sig-
nal. The AD1890/AD1891 dynamically alter the low-pass filter
cutoff frequency smoothly and slowly, so that real-time varia-
tions in the sample rate ratio are possible without degradation of
the audio quality.
The AD1890/AD1891 have a pin selectable slow- or fast-settling
mode. This mode determines how quickly the ASRCs adapt to a
change in either the input sample clock frequency (FSIN) or the
output sample clock frequency (FSOUT). In the slow-settling
mode, the control loop which computes the ratio between FSIN
and FSOUT settles in approximately 800 ms and begins to reject
jitter above 3 Hz. The slow-settling mode offers the best signal
quality and the greatest jitter rejection. In the fast-settling mode,
the control loop settles in approximately 200 ms and begins to
reject jitter above 12 Hz. The fast-settling mode allows rapid,
real time sample rate changes to be tracked without error, at the
expense of some narrow-band noise modulation products on the
output signal.
The AD1890 also has a pin selectable, short or long group delay
mode. This pin determines the depth of the First-In, First-Out
(FIFO) memory which buffers the input data samples before
they are processed by the FIR convolver. In the short mode, the
group delay is approximately 700 μs. The ASRC is more sensi-
tive to sample rate changes in this mode (i.e., the pointers which
manage the FIFO are more likely to cross and become momen-
tarily invalid during a sample rate step change), but the group
delay is minimized. In the long mode, the group delay is ap-
proximately 3 ms. The ASRC is tolerant of large dynamic
sample rate changes in this mode, and it should be used when
the device is required to track fast sample rate changes, such as
in varispeed applications. The AD1891 features the short group
delay mode only. In either device, if the read and write pointers
that manage the FIFO cross (indicating underflow or overflow),
the ASRC asserts the mute output (MUTE_O) pin HI for 128
output clock cycles. If MUTE_O is connected to the mute input
(MUTE_I) pin, as it normally should be, the serial output will
be muted (i.e., all bits zero) during this transient event.
The AD1890/AD1891 are fabricated in a 0.8μm single poly,
double metal CMOS process and are packaged in a 0.6" wide
28-pin plastic DIP and a 28-pin PLCC. The AD1890/AD1891
operate from a +5 V power supply over the temperature range of
0°C to +70°C.
AD1890/AD1891 PIN LIST
Serial Input Interface
Serial Output Interface
Input Control SignalsNOTEThe beginning of valid data will be delayed by one BLCK_I if MSBDEL_I is selected (HI).
Group DelayIntuitively, the time interval required for a full-level input pulse
to appear at the converter’s output, at full level, expressed in
milliseconds (ms). More precisely, the derivative of radian phase
with respect to radian frequency at a given frequency.
Transport DelayThe time interval between when an impulse is applied to the
converters input and when the output starts to be affected by
this impulse, expressed in milliseconds (ms). Transport delay is
independent of frequency.
DEFINITIONS
Dynamic RangeThe ratio of a near full-scale input signal to the integrated noise
in the passband (0 to ≈20 kHz), expressed in decibels (dB). Dy-
namic range is measured with a –60 dB input signal and
“60dB” arithmetically added to the result.
Total Harmonic Distortion + NoiseTotal Harmonic Distortion plus Noise (THD+N) is defined as
the ratio of the square root of the sum of the squares of the val-
ues of the harmonics and noise to the rms value of a sinusoidal
input signal. It is usually expressed in percent (%) or decibels.
Interchannel Phase DeviationDifference in input sampling times between stereo channels, ex-
pressed as a phase difference in degrees between 1 kHz inputs.
AD1890/AD1891
Output Control Signals
Miscellaneous
Power Supply ConnectionsNOTEThe beginning of valid data will be delayed by one BCLK_O if MSBDEL_O is selected (Hl).
THEORY OF OPERATIONThere are at least two logically equivalent methods of explaining
the concept of asynchronous sample rate conversion: the high
speed interpolation/decimation model and the polyphase filter
bank model. Using the AD1890 and AD1891 SamplePorts does
not require understanding either model. This section is included
for those who wish a deeper understanding of their operation.
Interpolation/Decimation ModelIn the high speed interpolation/decimation model, illustrated in
Figure 1, the sampled data input signal (Plot A in Figure 1) is
interpolated at some ratio (IRATIO) by inserting IRATIO-1
zero valued samples between each of the original input signal
samples (Plot B in Figure 1). The frequency domain characteris-
tics of the input signal are unaltered by this operation, except
that the zero-padded sequence is considered to be sampled at a
frequency which is the product of original sampling frequency
multiplied by IRATIO.
The zero-padded values are fed into a digital FIR low-pass filter
(Plot C in Figure 1) to smooth or integrate the sequence, and
limit the bandwidth of the filter output to 20 kHz. The interpo-
lated output signal has been quantized to a much finer time
scale than the original sequence. The interpolated sequence is
then passed to a zero-order hold functional block (physically
implemented as a register, Plot D in Figure 1) and then asyn-
chronously resampled at the output sample frequency (Plot E in
Figure 1). This resampling can be thought of as a decimation
operation since only a very few samples out of the great many
interpolated samples are retained. The output values represent
the “nearest” values, in a temporal sense, produced by the inter-
polation operation. There is always some error in the output
sample amplitude due to the fact that the output sampling
switch does not close at a time that exactly corresponds to a
point on the fine time scale of the interpolated sequence. How-
ever, this error can be made arbitrarily small by using a very
large interpolation ratio. The AD1890/AD1891 SamplePort
ASRCs use an equivalent IRATIO of 65,536 to provide 16-bit
accuracy (≈ –96 dB THD+N) across the 0 to 20 kHz audio
band.
The number of FIR filter taps and associated coefficients is
approximately 4 million. The equivalent FIR filter convolution
frequency (or “upsample” frequency) is 3.2768 GHz, and the
fine time scale has resolution of about 300 ps. Various propri-
etary efficiencies are exploited in the AD1890/AD1891 ASRCs
to reduce the complexity and throughput requirements of the
hardware implied by this interpolation/decimation model.
INPUT
SIGNAL
OUTPUT
SIGNAL
TIME
AMPFigure 1. Interpolation/Decimation Model—Time Domain View
AD1890/AD1891
Polyphase Filter Bank ModelAlthough less intuitively understandable than the interpolation/
decimation model, the polyphase filter bank model is useful to
explore because it more accurately portrays the operation of the
actual AD1890/AD1891 SamplePort hardware. In the polyphase
filter bank model, the stored FIR filter coefficients are thought
of as the impulse response of a highly oversampled 0 to 20 kHz
low-pass prototype filter, as shown in Figure 2. If this low-pass
filter is oversampled by a factor of N, then it can be conceptu-
ally decomposed into N different “subfilters,” each filter consist-
ing of a different subset of the original set of impulse response
samples. If the temporal position of each of the subfilters is
maintained, then they can be summed to recreate the original
oversampled impulse response. Since the original impulse
response is highly oversampled, the more sparsely sampled
subfilters still individually meet the Nyquist criterion (i.e., they
are adequately sampled). The baseband magnitude and phase
responses of the subfilters are identical. The out-of-band (i.e.,
alias) regions of the subfilters however have phase responses
which are shifted relative to one another, in a manner that
causes them to cancel when they are summed.
The subfilter coefficients are then aligned to the left, as shown
in Figure 3, so that the first coefficient of each subfilter is
aligned to the first point on a coarse time scale. (This concep-
tual step accounts for how the hardware implementation is able
to operate at the slower rate corresponding to the coarse time
scale.) Each subfilter has been shifted in time by a different
amount, and though they still share identical magnitude
responses, they now have in-band phase responses which have
fractionally different slopes (i.e., group delays).
AMP
TIME
OVERSAMPLED
LOW PASS FILTER
IMPULSE RESPONSE
DECOMPOSED INTO
FOUR SUBFILTERS
PHASE
0 Deg
1/4Fs1/2Fs3/4FsFs
FREQ
AMP
1/4Fs1/2Fs3/4FsFs
1/4Fs1/2Fs3/4FsFs
1/4Fs1/2Fs3/4FsFs
1/4Fs1/2Fs3/4FsFsFigure 2.Four Polyphase Subfilters in the Time and Frequency Domains
AMP
TIME
FREQsin/2sin/2sin/2sin/2sin/2
PHASE
DELAY = NOMINAL
DELAY = NOMINAL
DELAY = NOMINAL – .25/Fsin
DELAY = NOMINAL – .5/Fsin
DELAY = NOMINAL – .75/FsinFigure 3. Four Polyphase Subfilters Realigned to Coarse Time Grid
Figure 4.Polyphase Filter Bank Model—Conceptual Block
Diagram
The full set of subfilters can be considered to form a parallel
bank of “polyphase” filters which have decrementing, linear
phase group delays. All of the polyphase filters conceptually pro-
cess the input signal simultaneously, as illustrated in Figure 4, at
the input sample rate.
AD1890/AD1891Asynchronous sample rate conversion under the polyphase filter
bank model is accomplished by selecting the output of a particu-
lar polyphase filter on the basis of the temporal relationship be-
tween the input sample clock and the output sample clock
events. Figure 5 shows the desired filter group delay as a func-
tion of the relative time difference between the current output
sample clock and the last input sample clock. If an output
sample is requested late in the input sample period, then a short
filter delay is required, and if an output sample is requested
early in the input sample period, then a long filter delay is re-
quired. This nonintuitive result arises from the fact that FIR fil-
ters always produce some delay, so that selecting a filter with
shorter delay moves the interpolated sample closer to the newest
input sample.
A short delay corresponds to a large offset into the dense FIR
filter coefficient array, and a long delay corresponds to a small
offset. Note that because the output sample clock can arrive at
any arbitrary time with respect to the input sample clock, the
selection of a polyphase filter with which to convolve the input
sequence occurs on every output sample clock event. Occasion-
ally the FIFO which holds the input sequence in the FIR con-
volver is either not incremented, or incremented by two between
output sample clocks (see periods A and B in Figure 5); this
happens more often when the input and output sample clock
frequencies are dissimilar than when they are close together.
However, in this situation, an appropriate polyphase filter is
selected to process the input signal, and thus an accurate output
sample is computed. Input and output samples are not skipped
or repeated (unless the input FIFO underflows or overflows), as
is the case in some other sample rate converter implementations.
To obtain an accurate conversion, a large number of polyphase
filters are needed. The AD1890/AD1891 SamplePorts use the
equivalent of 65,536 polyphase filters to achieve their profes-
sional audio quality distortion and dynamic range specifications.
Sample Clock TrackingIt should be clear that, in either model, the correct computation
of the ratio between the input sample rate (as determined from
the left/right input clock, LR_I) and the output sample rate (as
determined from the left/right output clock, LR_O) is critical to
the quality of the output data stream. It is straightforward to
compute this ratio if the sample rates are fixed and synchronous;
the challenge is to accurately track dynamically varying and
asynchronous sample rates, as well as to account for jitter.
Figure 5.Input and Output Clock Event Relationship
The AD1890/AD1891 SamplePorts solve this problem by
embedding the ratio computation circuit within a digital servo
control loop, as shown in Figure 6. This control loop includes
special provisions, to allow for the accurate tracking of dynami-
cally changing sample rates. The outputs of the control loop are
the starting read addresses for the input data FIFO and the filter
coefficient ROM. These start addresses are used by the FIFO
and ROM address generators, as shown in Figure 6.
The input data FIFO write address is generated by a counter
which is clocked by the input sample clock (i.e., LR_I). It is very
important that the FIFO read address and the FIFO write ad-
dress do not cross, as this means that the FIFO has either
underflowed or overflowed. This consideration affects the
choice of settling time of the control loop. When a step change
in the sample rate occurs, the relative positions of the read and
write addresses will change while the loop is settling. A fast set-
tling loop will act to keep the FIFO read and write addresses
separated better than a slow settling loop. The AD1890/
AD1891 include a user selectable pin (SETLSLW) to set the
loop settling time that essentially changes the coefficients of the
digital servo control loop filter. The state of the SETLSLW pin
can be changed on-the-fly but is normally set and forgotten.
